Frequency

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A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS

A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS 150 150
Author(s): Kshitiz Tyagi, Kunbo Ma, Joung Won Park, Behzad Razavi

Abstract:

We present a transceiver architecture for single-ended PAM4 signaling, introducing an inverter-based active-inductor-terminated front end that obviates the need for further equalizer stages, substantially reducing power and area. Realized in 28-nm CMOS technology, the four-lane link operates at 64 Gb/s/pin with a bit error rate (BER) less than $10{^{-12}}$ …

Published in: IEEE Solid-State Circuits Letters
Page(s): 230 – 233
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3721808
Publisher: IEEE

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A 9-GHz Digital Fractional-N PLL with Dynamic-Threshold DTC

A 9-GHz Digital Fractional-N PLL with Dynamic-Threshold DTC 150 150
Author(s): Daxu Zhang, Yuncheng Zhang, Zezheng Liu, Yuang Xiong, Wenqian Wang, Duo Li, Minzhe Tang, Dongfan Xu, Dingxin Xu, Kazuaki Kunihiro, Hiroyuki Sakai, Kenichi Okada

Abstract:

This letter presents a fractional-N digital phase-locked loop (DPLL) employing a dynamic-threshold digital-to-time converter (DT-DTC). By dynamically adjusting the comparator threshold voltage, the proposed DT-DTC mitigates delay nonlinearity without digital predistortion (DPD). A quadrature-VCO (QVCO) generates quadrature phases for a multi-phase clock generator (MPCG). The QVCO-based MPCG with skew calibration …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3725284
Publisher: IEEE

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A Broadband Class-E Power Amplifier with Compact Harmonic Suppression Susceptance Compensation Load Network in 110-nm CMOS

A Broadband Class-E Power Amplifier with Compact Harmonic Suppression Susceptance Compensation Load Network in 110-nm CMOS 150 150
Author(s): Kai Yue, Yubing Li, Yujia Chen, Xiuping Li

Abstract:

This letter presents a compact Class-E power amplifier (PA) with broadband and enhanced harmonic suppression performance. The harmonic suppression susceptance compensation (HSSC) Class-E load network is proposed and analyzed to simultaneously achieve broadband fundamental matching and harmonic suppression. Despite its sixth-order LC complexity, the proposed HSSC Class-E load network is …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3725042
Publisher: IEEE

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An H-Band Continuous Broadband RF-Domain Quadrature Receiver Using a Harmonic-Enhanced LO Generator in 65-nm CMOS

An H-Band Continuous Broadband RF-Domain Quadrature Receiver Using a Harmonic-Enhanced LO Generator in 65-nm CMOS 150 150
Author(s): Weiping Wu, Xun Bao, Jingze Wang, Shi Chen, Shulan Chen, Yan Wang, Lei Zhang

Abstract:

This article presents an $H$ -band CMOS receiver chipset that covers a wide frequency range of 228–324 GHz, supporting the entire band of IEEE Std. 802.15.3d. The proposed receiver employs an RF-domain quadrature mixer-first architecture to alleviate the design burden of quadrature local oscillator (LO) signal generation in $H$ -band, which …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 4584 – 4599
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3697557
Publisher: IEEE

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A 6.3–18.4 GHz I/Q Receiver With RF and LO Path Reconfigurability for 6G FR3 Applications in 22-nm FD-SOI

A 6.3–18.4 GHz I/Q Receiver With RF and LO Path Reconfigurability for 6G FR3 Applications in 22-nm FD-SOI 150 150
Author(s): Haisu Ju, Yingtao Zou, Gabriel M. Rebeiz

Abstract:

This article presents a 6.3–18.4 GHz in-phase and quadrature (I/Q) direct down-conversion receiver featuring reconfigurability in both the radio frequency (RF) and local oscillator (LO) paths. The receiver comprises a multi-band reconfigurable RF front-end, double-balanced passive I/Q mixers, an I/Q LO generation network with a tunable I/Q …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 4558 – 4571
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3698025
Publisher: IEEE

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A 31.5–36-GHz Low-Spur Digitally Assisted Gain-Boosting Charge-Sharing Locking PLL Achieving 54-fs RMS Jitter

A 31.5–36-GHz Low-Spur Digitally Assisted Gain-Boosting Charge-Sharing Locking PLL Achieving 54-fs RMS Jitter 150 150
Author(s): Chawin Khongprasongsiri, Sayan Kumar, Patchara Sawakewang, Robert Bogdan Staszewski, Teerachot Siriburanon

Abstract:

This article presents a 31.5–36 GHz digitally assisted gain-boosting (GB) charge-sharing locking (CSL) phase-locked loop (PLL) that achieves record-low reference spurs while maintaining sub-60 fs integrated jitter. In conventional CSL PLLs, reference spur suppression is fundamentally traded against loop bandwidth, whereas ping-pong CSL (PP-CSL) approaches typically require complex duty-cycle calibration. The …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721352
Publisher: IEEE

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A Calibration-Free Frequency-Scalable ΔΣ ADC Incorporating PVT-Robust Dynamic Integration

A Calibration-Free Frequency-Scalable ΔΣ ADC Incorporating PVT-Robust Dynamic Integration 150 150
Author(s): Tohru Kaneko, Hideaki Ishida, Yuzuru Yamaki, Satoshi Takehara, Un-Ku Moon

Abstract:

This article summarizes a calibration-free, frequency-scalable $Delta Sigma $ analog-to-digital converter (ADC) which employs dynamic open-loop integrators for low-power sensing systems. The integrators use a capacitive degeneration scheme to obtain an integration factor determined by a capacitor ratio. To enhance process-voltage-temperature (PVT) robustness, bottom-plate level shift (BPLS) and a timer are …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3719645
Publisher: IEEE

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A 300-μW BLE-Compliant Packet-Based Data-Agnostic Clock-Harvesting RX Achieving −85/−70 dBm Sensitivity for ±40/±15 ppm Accuracy

A 300-μW BLE-Compliant Packet-Based Data-Agnostic Clock-Harvesting RX Achieving −85/−70 dBm Sensitivity for ±40/±15 ppm Accuracy 150 150
Author(s): Maryam Dodangeh, Mark S. Oude Alink, Jan Prummel, Bram Nauta

Abstract:

An ultralow-power Bluetooth low energy (BLE)-compliant crystal-less clock-harvesting receiver is presented that uses the BLE advertising packets (APs) to calibrate an on-chip frequency reference with ±400 ppm initial frequency offset. The proposed front-end, fabricated in 22 nm FDSOI, is capable of pushing the frequency accuracy of the reference further to below ±40/±15 …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3718973
Publisher: IEEE

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A 58.9–73.7-GHz Quadrature Dual-Core Class-F₃,₅ Oscillator With Tail-Assisted Implicit Quintupling

A 58.9–73.7-GHz Quadrature Dual-Core Class-F₃,₅ Oscillator With Tail-Assisted Implicit Quintupling 150 150
Author(s): Yevhenii Mormul, Patchara Sawakewang, Sayan Kumar, Chawin Khongprasongsiri, Teerachot Siriburanon, Robert Bogdan Staszewski

Abstract:

We introduce a new class-F3,5 oscillator topology that enables quadrature operation by duplicating a conventional class-F3 oscillator core and electromagnetically coupling the two cores through a pair of additional coils feeding source terminals of the $g_{m}$ transistors. The coupling network enhances the fifth-harmonic component, enabling efficient extraction and quadrature …

Published in: IEEE Solid-State Circuits Letters
Page(s): 198 – 201
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3699799
Publisher: IEEE

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