FeFETs

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DTCO of NOR-Type IGZO FeFETs for 3-D Heterogeneous AI Memories: A Read-Centric Perspective

DTCO of NOR-Type IGZO FeFETs for 3-D Heterogeneous AI Memories: A Read-Centric Perspective 150 150
Author(s): Yang Xiang, Zhuo Chen, Nicolò Ronchi, Arvind Sharma, Fernando García-Redondo, Subhali Subhechha, Attilio Belmonte, Maarten Rosmeulen, Gouri Sankar Kar, Dwaipayan Biswas, Jan Van Houdt

Abstract:

InGaZnO (IGZO)-channel FeFETs have attracted notable interest thanks to recent advances in endurance, opening up their application space for read-dominated AI memory tiers. This work evaluates the viability of NOR-type IGZO FeFETs for 3-D heterogeneous AI memories from a read-centric design-technology co-optimization (DTCO) perspective, spanning on-chip back-end-of-line (BEOL) random-access …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 249 – 255
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740054
Publisher: IEEE

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FeFET-Based CMOS Current Starvation Programmable Delay Element

FeFET-Based CMOS Current Starvation Programmable Delay Element 150 150
Author(s): Albi Mema, Simon Thomann, Hussam Amrouch

Abstract:

Programmable delay elements (PDEs) are crucial circuit building blocks that enable precise timing adjustments of signal transitions. They are used in various critical applications, like time-to-digital converters. They are often used to mitigate aging by clock skew tuning postfabrication. However, typical CMOS PDE designs require many transistors while still offering …

Published in: IEEE Solid-State Circuits Letters
Page(s): 166 – 169
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3692304
Publisher: IEEE

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A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC

A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC 150 150
Author(s): Vaidehi Garg, Jianwei Jia, Omkar Phadke, Shimeng Yu

Abstract:

Compute-in-memory (CIM) using emerging nonvolatile memory devices is a promising candidate for energy-efficient deep neural network (DNN) inference at the edge. Ferroelectric field-effect transistors (FeFETs) have recently gained attention as nonvolatile, CMOS-compatible devices with a higher on/off ratio and lower read and write energy compared to resistive random-access memory (…

Published in: IEEE Solid-State Circuits Letters
Page(s): 13 – 16
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3640522
Publisher: IEEE

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1.58-b FeFET-Based Ternary Neural Networks: Achieving Robust Compute-In-Memory With Weight-Input Transformations

1.58-b FeFET-Based Ternary Neural Networks: Achieving Robust Compute-In-Memory With Weight-Input Transformations 150 150
Author(s): Imtiaz Ahmed, Akul Malhotra, Revanth Koduru, Sumeet Kumar Gupta

Abstract:

Ternary weight neural networks (TWNs), with weights quantized to three states (−1, 0, and 1), have emerged as promising solutions for resource-constrained edge artificial intelligence (AI) platforms due to their high energy efficiency with acceptable inference accuracy. Further energy savings can be achieved with TWN accelerators utilizing techniques such as compute-in-memory (CiM) and …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 157 – 165
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3621160
Publisher: IEEE

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A Bit-Cell Failure Analysis Framework for Ferroelectric Field-Effect Transistor-Based Memories

A Bit-Cell Failure Analysis Framework for Ferroelectric Field-Effect Transistor-Based Memories 150 150
Author(s): Jianze Wang, Wei Zhang, Xuanyao Fong

Abstract:

The ferroelectric field-effect transistor (FeFET) is a promising memory device technology due to desirable attributes, such as fast access times, high memory cell density, good endurance, compatibility with CMOS process, and impressive scalability. While previous research has explored the impact of process variations at the device level, their effects on …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 123 – 130
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3616007
Publisher: IEEE

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FIMA: A Scalable Ferroelectric Compute-in-Memory Annealer for Accelerating Boolean Satisfiability

FIMA: A Scalable Ferroelectric Compute-in-Memory Annealer for Accelerating Boolean Satisfiability 150 150
Author(s): Mohammad Khairul Bashar, T. H. Pantha, Z. Li, M. Farasat, S. Datta, V. Narayanan, S. Dutta, N. Shukla

Abstract:

In-memory compute kernels present a promising approach for addressing data-centric workloads. However, their scalability—particularly for computationally intensive tasks solving combinatorial optimization problems such as Boolean satisfiability (SAT), which are inherently difficult to decompose—remains a significant challenge. In this work, we propose a ferroelectric nonvolatile memory (NVM)-based compute-in-memory …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 81 – 89
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3603942
Publisher: IEEE

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Reconfigurable Ferroelectric Bandpass Filter With Low-Frequency Noise Analysis for Intracardiac Electrogram Monitoring

Reconfigurable Ferroelectric Bandpass Filter With Low-Frequency Noise Analysis for Intracardiac Electrogram Monitoring 150 150
Author(s): Jianwei Jia, Zhenge Jia, Omkar Phadke, Yiyu Shi, Shimeng Yu

Abstract:

Implantable cardioverter defibrillators (ICDs) provide real-time monitoring and immediate defibrillation for life-threatening arrhythmias. However, the intracardiac electrogram (IEGM) acquisition of ICDs faces stringent constraints, including power consumption, low-frequency noise, and patient-specific physiological variability. This article introduces an ultralow-power, high-resolution, reconfigurable three-stage bandpass filter designed specifically for IEGM, utilizing ferroelectric field-effect …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 67 – 73
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3584711
Publisher: IEEE

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