Engines

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A 27.5–28.5 mJ/Frame 3-D Gaussian Rendering Processor With Spherical Beta Illumination and Mixed-Precision Computation Path

A 27.5–28.5 mJ/Frame 3-D Gaussian Rendering Processor With Spherical Beta Illumination and Mixed-Precision Computation Path 150 150
Author(s): Cheng Nian, Xiaorui Mo, Jiaqi Zhang, Fasih Ud Din Farrukh, Jiaying Peng, Fei Chen, Chun Zhang

Abstract:

This letter presents a 3-D Gaussian rendering processor that integrates a spherical beta (SB) illumination module with a mixed-precision rendering engine to enable energy-efficient novel-view synthesis on edge devices. SB replaces spherical harmonics (SH) with a hardware-efficient kernel implemented using a pipelined fixed-point piecewise linear (PWL) power unit. The pipeline …

Published in: IEEE Solid-State Circuits Letters
Page(s): 113 – 116
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3676726
Publisher: IEEE

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MITTA: A Multi-Task Transformer Accelerator With Mixed Precision Structured Sparsity and Hierarchical Task-Adaptive Power Management

MITTA: A Multi-Task Transformer Accelerator With Mixed Precision Structured Sparsity and Hierarchical Task-Adaptive Power Management 150 150
Author(s): Qirui Zhang, Zichen Fan, Pierre Abillama, Sara Shoouri, Jungho Lee, Chien-Wei Tseng, Changwoo Lee, Wei Meng, Hun-Seok Kim, David Blaauw, Dennis Sylvester

Abstract:

This article presents MITTA, the first silicon-proven transformer accelerator optimized for multi-task inference across both natural language processing (NLP) and image processing domains. MITTA accelerates a task-sharing algorithm that minimizes sub-task computation by reusing both activations and weights from a shared base task, requiring only sparse delta computation for sub-tasks. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3669815
Publisher: IEEE

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Adelia: A 4-nm LLM Processing Unit With Streamlined Dataflow and Dual-Mode Parallelism for Maximizing Hardware Efficiency

Adelia: A 4-nm LLM Processing Unit With Streamlined Dataflow and Dual-Mode Parallelism for Maximizing Hardware Efficiency 150 150
Author(s): Sukbin Lim, Jung-Hoon Kim, Seungjae Moon, Junseo Cha, Dongjin Seo, Jongho Kim, Hunjong Lee, Jinwon Lee, Joo-Young Kim

Abstract:

The proliferation of large language models (LLMs) as cross-domain foundation models is fueled by aggressive scaling in both parameter counts and inference-time computation. The emergence of sophisticated reasoning models further accelerates this trend, demanding longer context windows and escalating the computational and memory burdens of inference. A fundamental challenge arises …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1513 – 1525
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663603
Publisher: IEEE

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A 54- $\\mu$ W Design-Agnostic Clock, Voltage, and EM-Pulse Fault-Injection Attack Detection Using Time-to-Voltage Conversion

A 54- $\\mu$ W Design-Agnostic Clock, Voltage, and EM-Pulse Fault-Injection Attack Detection Using Time-to-Voltage Conversion 150 150
Author(s): Yudhajit Ray, Archisman Ghosh, Sarthak Antal, Shreyas Sen

Abstract:

This article presents a state-of-the-art design-agnostic clock, voltage, and electromagnetic pulse (EMP)-based fault-injection attack (FIA) detector. The efficient conversion of time-to-voltage information by integrating amplifiers transforms the time anomaly into the voltage domain, enabling its detection at a lower power consumption. The clock-glitch detector design consumes only $53~\mu $ W …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3655593
Publisher: IEEE

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