Design methodology

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A Continuous-Time Incremental Zoom ADC With Extended Quantization, Easy-to-Drive Capacitive Input and Deadband-Embedded Gm-C Loop Filter

A Continuous-Time Incremental Zoom ADC With Extended Quantization, Easy-to-Drive Capacitive Input and Deadband-Embedded Gm-C Loop Filter 150 150
Author(s): Chaoyang Xing, Yilu Cui, Yi Zhong, Nan Sun, Lu Jie

Abstract:

This article presents a continuous-time (CT) analog-to-digital converter (ADC) featuring an incremental zoom with extended quantization architecture. The proposed MASH topology comprises an 8-bit oversampled successive-approximation register (SAR) ADC as the first stage, a 1-bit incremental CT delta-sigma modulator (CT-DSM) as the second stage, and a 12-bit Nyquist SAR ADC …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3717666
Publisher: IEEE

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Raisu: A Radiation-Tolerant Neuromorphic Imager With In-Pixel Self-Healing and Unified Spiking Processing for Spaceborne Vision

Raisu: A Radiation-Tolerant Neuromorphic Imager With In-Pixel Self-Healing and Unified Spiking Processing for Spaceborne Vision 150 150
Author(s): Quan Cheng, Qiufeng Li, Zhengke Yang, Zhen Kong, Gaoqiang Niu, Yuan Liang, Jiamin Li, Jeong Hoan Park, Wang Liao, Hiromitsu Awano, Takashi Sato, Longyang Lin, Masanori Hashimoto

Abstract:

Spaceborne imaging systems operate under severe radiation and energy constraints, where single-event effects (SEEs), total ionizing dose (TID), and displacement damage dose (DDD) critically degrade reliability and performance. This work presents a radiation-tolerant neuromorphic imager prototype featuring a fully spike-based neuromorphic vision architecture with in-pixel self-healing capability and an integrated …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715724
Publisher: IEEE

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A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS

A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS 150 150
Author(s): Saideep Cherukuri, N. V. Kidambi, W. C. Wang, I. Chakraborty, S. Zhang, L. Shamieh, J. B. Steinberg, S. Mukhopadhyay

Abstract:

Mixed-signal CIM (MS-CIM) faces bit-cell nonlinearity, poor linearity at high frequency, and throughput limits. We present a hybrid pipelined current-domain MS-CIM macro featuring bit-cell matched linearization interface (BMLI) and loop-unrolled successive approximation refinement (SAR) ADC fabricated in 28-nm CMOS. A $256{\,}\times {\,}256$ SRAM array with 8-bit inputs, 8-bit weights achieve 10.16-TOPS …

Published in: IEEE Solid-State Circuits Letters
Page(s): 174 – 177
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697990
Publisher: IEEE

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A Tunable RF Self-Interference Canceller With Highly Accelerated, Machine-Learning-Based Adaptation for Full-Duplex Radio Applications

A Tunable RF Self-Interference Canceller With Highly Accelerated, Machine-Learning-Based Adaptation for Full-Duplex Radio Applications 150 150
Author(s): Xichen Li, Ahmed Refaat Aboulsaad, Elpida Karapepera, Yi-Hsiang Huang, Po-Hao Cheng, Charles Chien, Jacques Christophe Rudell

Abstract:

Future full-duplex (FD) radio systems require highly tunable self-interference (SI) cancellers with rapid adaptation to mitigate dynamic SI profiles in wireless environments. This article presents a 2.4-GHz RF SI canceller chip with extensive tuning capabilities that operates with a machine-learning (ML)-augmented adaptation loop for FD transceivers. The proposed design …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715631
Publisher: IEEE

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A 12 b 180-MS/s Pipelined-SAR ADC With a Low-Power Calibration-Free RA and Hardware-Efficient SAR Logic

A 12 b 180-MS/s Pipelined-SAR ADC With a Low-Power Calibration-Free RA and Hardware-Efficient SAR Logic 150 150
Author(s): Guo Wei, Rui Zhang, Fule Li, Hanjun Jiang, Zhihua Wang

Abstract:

This letter presents a 12-bit, 180-MS/s pipelined-SAR ADC in 65-nm CMOS. To eliminate the complex interstage gain-error calibration for a fast-response characteristic, a high-gain residue amplifier (RA) featuring a two-stage gain-boosting architecture is proposed. By removing the tail current, the RA significantly alleviates slew-rate and voltage headroom limitations. The …

Published in: IEEE Solid-State Circuits Letters
Page(s): 186 – 189
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697220
Publisher: IEEE

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FSL-HDnn: A 40-nm Few-Shot On-Device Learning Accelerator With Integrated Feature Extraction and Hyperdimensional Computing

FSL-HDnn: A 40-nm Few-Shot On-Device Learning Accelerator With Integrated Feature Extraction and Hyperdimensional Computing 150 150
Author(s): Weihong Xu, Chang Eun Song, Haichao Yang, Leo Liu, Meng-Fan Chang, Carlos H. Diaz, Tajana Rosing, Mingu Kang

Abstract:

This article introduces FSL-HDnn, an energy-efficient accelerator that implements the end-to-end pipeline of feature extraction (FE) and on-device few-shot learning (FSL). The accelerator addresses fundamental challenges of on-device learning (ODL) for resource-constrained edge applications through two synergistic modules: a parameter-efficient feature extractor (FE) employing weight clustering and an FSL classifier …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3709217
Publisher: IEEE

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An Extendable Wideband Band-Divided SPnT Switch Topology Based on a Reconfigurable Pole-to-Throw Network

An Extendable Wideband Band-Divided SPnT Switch Topology Based on a Reconfigurable Pole-to-Throw Network 150 150
Author(s): Zhaowu Wang, Hao Ning, Xinyan Li, Ze Yu, Qiliang Li, Xiaochen Tang, Yong Wang

Abstract:

This article presents an extendable wideband band-divided SP $n$ T switch topology based on a reconfigurable pole-to-throw network (RPTN). Compared to conventions, it mitigates the loss degradation resulting from complex signal routing in advanced RF front-ends. This is enabled by the RPTN, which divides the throws into low-/mid-/high-band (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3711644
Publisher: IEEE

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A Three-Level Dual-Path Hybrid Buck Converter With Mitigated Capacitive Current and Seamless DVS Across a Wide Output Voltage Range

A Three-Level Dual-Path Hybrid Buck Converter With Mitigated Capacitive Current and Seamless DVS Across a Wide Output Voltage Range 150 150
Author(s): Jae-Hyun Kim, Jun-Gi Lee, Hyunki Han, Hyun-Sik Kim

Abstract:

This article presents a three-level dual-path (TLDP) buck converter tailored for mobile application processors (APs) with a 1.8-V input and 0.4–1.5-V output range. Conventional buck (CB) and multi-level buck (MLB) converters suffer from prohibitive DC resistance ( $R_{\mathrm {DCR}}$ ) losses in compact inductors as load current increases. Although various multi-path …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3710310
Publisher: IEEE

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Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells

Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells 150 150
Author(s): Daniel S. Truesdell, Jacob Breiholz, Benton H. Calhoun

Abstract:

This article investigates dynamic leakage-suppression (DLS) logic for minimum-power operation in digital circuits. The DLS logic family uses a strong intrinsic subthreshold leakage reduction technique and is an emerging approach for computing applications that prioritize low active power at or beneath the nW-level. We analytically model the key operating characteristics …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3709741
Publisher: IEEE

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