Design methodology

  • No Comments

A Low-Power MRAM-Based Nonvolatile Flip-Flop Architecture for Register and System Applications

A Low-Power MRAM-Based Nonvolatile Flip-Flop Architecture for Register and System Applications 150 150
Author(s): Bayartulga Ishdorj, Taehui Na

Abstract:

This work presents a minimal nonvolatile flip-flop (NVFF) hybrid architecture and an NV static contention-free differential FF (nvSCDFF) cell that reduces the overhead associated with replicated NV circuitry in conventional in situ NVFFs while enabling low power. By using only one NVFF per column and compact SCDFF-based volatile flip-flops (FFs), …

Published in: IEEE Solid-State Circuits Letters
Page(s): 206 – 209
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3713204
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM

Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM 150 150
Author(s): Yutian Zhang, Jiaquan Fang, Khawar Sarfraz, Mansun Chan

Abstract:

This work shows that a multitier complementary FET (CFET) static random access memory (SRAM) can decouple the area term from PPA-oriented transistor sizing. A topology-aware layout design is used to construct orthogonal and point-symmetric multitier CFET SRAM cells under 1-nm-class design rules, enabling high-density (HD), high-performance (HP), and high-current (HC) …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 159 – 166
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3709007
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Self-Heating and Parasitic Effects in Multi-Tier CFET Design

Self-Heating and Parasitic Effects in Multi-Tier CFET Design 150 150
Author(s): Sufia Shahin, Mahdi Benkhelifa, Yogesh Singh Chauhan, Hussam Amrouch

Abstract:

In this article, we study the impact of self-heating effects (SHEs) and middle of line (MOL) and back-end of line (BEOL) induced parasitics on multi-tier CFET design, where multiple nanosheet devices are vertically stacked. We analyze and compare the four-tier complementary FET (CFET) design with the conventional two-tier CFET, using …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 153 – 158
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704373
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2

A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2 150 150
Author(s): Marco Pasotti, Riccardo Zurla, J. J. Bertolini Agnoletto, Emanuela Calvetti, Alessio Antolini, Andrea Lico, Giuseppe Desoli, Riccardo Vignali, Luca Iannelli, Luigi Croce, Francesco Zavalloni, Eleonora Franchi Scarselli, Alessandro Cabrini

Abstract:

In-memory computing (IMC) hardware accelerators for deep neural networks (DNNs) require storing a massive number of coefficients within a single computing macro to avoid performance degradation in multicore clusters. This aspect, often overlooked by common figures of merit (FoMs), can be effectively addressed by phase-change memory (PCM) technology, thanks to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 3193 – 3207
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3693894
Publisher: IEEE

View on IEEE Xplore

  • No Comments

TexCAC: A Direct-Textile-Attachable Microcontroller Integrating 2-MB MRAM for the Command and Control of Advanced Smart Textiles

TexCAC: A Direct-Textile-Attachable Microcontroller Integrating 2-MB MRAM for the Command and Control of Advanced Smart Textiles 150 150
Author(s): Jacob Mack, Qirui Zhang, He Wang, Yi Shen, Jeongtaek Chang, Heejin Yang, Anjali Agrawal, Zichen Fan, Braden Desman, Zane Lewis, Thomas Farrell, David Blaauw, Will Farrell, Jim Owens, Benton H. Calhoun, Dennis Sylvester

Abstract:

Advanced smart textiles (ASTs) are textile-integrated electronic systems that enable many applications, including healthcare, robotics, and IoT. ASTs contain a variety of electronic components to enable whole system functionality (batteries, sensors, SoCs, etc.), which all require orchestration from a central command-and-control (CAC) module. The primary functions of the CAC module …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 3307 – 3316
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3695482
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Open DRAM Model—Part I: Cross-Layer Device, Array, and Circuit Analysis With BL-to-BL Coupling Mitigation for 4F2 VCT DRAM

Open DRAM Model—Part I: Cross-Layer Device, Array, and Circuit Analysis With BL-to-BL Coupling Mitigation for 4F2 VCT DRAM 150 150
Author(s): Kiseok Lee, Seongkwang Lim, Suman Datta, Shimeng Yu

Abstract:

Dynamic random access memory (DRAM) scaling toward 4F2 vertical channel transistors (VCTs) fundamentally reshapes device, array, and circuit-level design tradeoffs. However, the lack of an open-source DRAM device model that is calibrated with recent industry trends prohibits broader innovations in the research community. In this work, we present an “Open …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 135 – 143
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704358
Publisher: IEEE

View on IEEE Xplore

  • No Comments

THz-TSI: A Terahertz Wireless Through-Silicon Interconnect Module for Advanced 3-D Integration Applications

THz-TSI: A Terahertz Wireless Through-Silicon Interconnect Module for Advanced 3-D Integration Applications 150 150
Author(s): Chen Jiang, Xiaodi Feng, Xiaohan Shen, Chixiao Chen, Qi Liu, Ming Liu, Ningsheng Xu

Abstract:

By vertically stacking device layers, advanced 3-D integration overcomes traditional planar scaling limits, delivering the bandwidth and power efficiency essential for modern artificial intelligence (AI) and high-performance computing (HPC) integrated systems. However, continued scaling of conventional through-silicon vias (TSVs) and microbumps presents critical bottlenecks due to inherent thermo-mechanical stress, complex …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3720291
Publisher: IEEE

View on IEEE Xplore

  • No Comments

APM-CIM: An Array Partition Multi-Macro CIM System With Dynamic Sparse Approximation for Neural Network Edge Applications

APM-CIM: An Array Partition Multi-Macro CIM System With Dynamic Sparse Approximation for Neural Network Edge Applications 150 150
Author(s): Bojun Zhang, Jinkai Wang, Zekun Wang, Xianan Zhu, Zhengkun Gu, Ziyuan Guo, Zhizhong Zhang, Kun Zhang, Weisheng Zhao, Yue Zhang

Abstract:

Computing-in-memory (CIM) has been widely investigated as a solution to the von Neumann bottleneck to reduce data transfer between memory and processor. However, existing CIM macros for neural network (NN) edge applications still suffer from high latency and energy consumption due to the correlation between data precision and the number …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3720241
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Continuous-Time Incremental Zoom ADC With Extended Quantization, Easy-to-Drive Capacitive Input and Deadband-Embedded Gm-C Loop Filter

A Continuous-Time Incremental Zoom ADC With Extended Quantization, Easy-to-Drive Capacitive Input and Deadband-Embedded Gm-C Loop Filter 150 150
Author(s): Chaoyang Xing, Yilu Cui, Yi Zhong, Nan Sun, Lu Jie

Abstract:

This article presents a continuous-time (CT) analog-to-digital converter (ADC) featuring an incremental zoom with extended quantization architecture. The proposed MASH topology comprises an 8-bit oversampled successive-approximation register (SAR) ADC as the first stage, a 1-bit incremental CT delta-sigma modulator (CT-DSM) as the second stage, and a 12-bit Nyquist SAR ADC …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3717666
Publisher: IEEE

View on IEEE Xplore

Search this website