Costs

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PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs
PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs 150 150
Author(s): Amitesh Sridharan, Jyotishman Saikia, Anupreetham, Fan Zhang, Jae-Sun Seo, Deliang Fan

Abstract:

We present a fully digital multiply and accumulate (MAC) in-memory computing (IMC) macro demonstrating one of the fastest flexible precision integer-based MACs to date. The design boasts a new bit-parallel architecture enabled by a 10T bit-cell capable of four AND operations and a decomposed precision data flow that decreases the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 102 – 105
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3369058
Publisher: IEEE

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Gordon Moore’s Journey: “Moore’s law” dissected
Gordon Moore’s Journey: “Moore’s law” dissected 150 150
Author(s): Ian Young

Abstract:

Gordon Moore may be best known for Moore’s law, which states that “the number of transistors on a microchip doubles every two years while the cost per transistor decreases.” While Moore’s law has been known since the 1960s, it is not well known what led Moore to make …

Published in: IEEE Solid-State Circuits Magazine
Page(s): 42 – 47
Year of Publication: 2024
Electronic ISSN: 1943-0590
DOI: 10.1109/MSSC.2023.3336168
Publisher: IEEE

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