Computer architecture

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A Millimeter-Wave Direct Digital Transmitter Using Multiphase Subharmonic Switching PA

A Millimeter-Wave Direct Digital Transmitter Using Multiphase Subharmonic Switching PA 150 150
Author(s): Soumya Mahapatra, Mostafa Ayesh, Ce Yang, Mayank Palaria, Shiyu Su, Aoyang Zhang, Mike Shuo-Wei Chen

Abstract:

This article presents a direct digital transmitter (TX) employing a multiphase subharmonic switching (MP-SHS) power amplifier (PA) to achieve both high peak and power back-off (PBO) efficiency with wide signal bandwidth. A phase-shifted subharmonic (SH) local oscillator (LO) divider is proposed to suppress SH spurs with minimal implementation overhead by …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3605564
Publisher: IEEE

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Fully Analog, Multi-Lag, RF Correlators for Code-Domain Radars Using Margin Propagation

Fully Analog, Multi-Lag, RF Correlators for Code-Domain Radars Using Margin Propagation 150 150
Author(s): Aswin Undavalli, Kareem Rashed, Abdul Rakib Hossain, Gert Cauwenberghs, Shantanu Chakrabartty, Arun Natarajan, Aravind Nagulu

Abstract:

We present a fully analog, multiplier-free, sampled-domain RF correlator to achieve high energy efficiency for radar workloads. The RF correlator employs a split-source follower architecture that leverages the margin propagation (MP) computing paradigm in the sampled domain. As a proof of concept, we implement a $256 \times 256$ fully analog cross correlator …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3602920
Publisher: IEEE

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ROZK: An Energy-Efficient DNN Accelerator Based on Reconfigurable NoC and Local Zero-Skipping

ROZK: An Energy-Efficient DNN Accelerator Based on Reconfigurable NoC and Local Zero-Skipping 150 150
Author(s): Heetak Kim, Yunpyo Hong, Byungsoo Kim, Jongsun Park

Abstract:

Zero-skipping is a famous technique to improve the energy efficiency of deep neural network (DNN) accelerators. When the zero-skipping is realized with encoded data using lossless compression, irregular and unpredictable size of data due to inconsistent compression rate incurs several design issues including: 1) load imbalance from irregularity of data stored …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3604814
Publisher: IEEE

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A 0.7-V Multiclass Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22-nm CMOS

A 0.7-V Multiclass Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22-nm CMOS 150 150
Author(s): Edoardo Baiesi Fietta, David Seebacher, Davide Ponton, Andrea Bevilacqua

Abstract:

This letter presents a multiclass, asymmetric digital Doherty power amplifier (DDPA) for Bluetooth low energy (BLE) applications, that achieves high efficiency at full-scale as well as at 8.6-dB back-off using a single 0.7-V supply voltage. The proposed DDPA is made of two power-combined switched-capacitor power amplifiers (SCPAs) and uses an …

Published in: IEEE Solid-State Circuits Letters
Page(s): 217 – 220
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3591570
Publisher: IEEE

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MIX-ACIM: A 28-nm Mixed-Precision Analog Compute-in-Memory With Digital Feature Restoration for Vector-Matrix Multiplication

MIX-ACIM: A 28-nm Mixed-Precision Analog Compute-in-Memory With Digital Feature Restoration for Vector-Matrix Multiplication 150 150
Author(s): Wei-Chun Wang, Shida Zhang, Laith Shamieh, Narasimha Vasishta Kidambi, Isha Chakraborty, Saibal Mukhopadhyay

Abstract:

A mixed-precision analog compute-in-memory (Mix-ACIM) is presented for mixed-precision vector-matrix multiplication (VMM). The design features an all-analog current-domain fixed-point (FxP) VMM with floating-point conversion and feature restoration. A 28 nm CMOS test chip shows 41 TOPS/W and 24 TOPS/mm2 for FxP (8-bit input/weight and 12-bit output) and 24.18 TFLOPS/W and 3.3 …

Published in: IEEE Solid-State Circuits Letters
Page(s): 213 – 216
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3590757
Publisher: IEEE

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A High-Density Low-Leakage and Low-Power Fully Voltage-Stacked SRAM for IoT Application

A High-Density Low-Leakage and Low-Power Fully Voltage-Stacked SRAM for IoT Application 150 150
Author(s): Sekeon Kim, Giseok Kim, Kyeongrim Baek, Keonhee Cho, Hyunjun Kim, Yeonho Jung, Dongwook Seo, Sangyeop Baeck, Sungjae Lee, Seong-Ook Jung

Abstract:

The general approach to suppress leakage in static random access memory (SRAM) is to use a low voltage ( $V_{text {L}}$ ), generated by a low-dropout regulator (LDO), as the cell supply voltage (CVDD) of SRAM array in the standby mode. However, the effectiveness of lowering CVDD is constrained by the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3582974
Publisher: IEEE

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A Simultaneous Dual-Carrier Transformer-Coupled Passive Mixer-First Receiver Front-End Supporting Blocker Suppression

A Simultaneous Dual-Carrier Transformer-Coupled Passive Mixer-First Receiver Front-End Supporting Blocker Suppression 150 150
Author(s): Jamie C. Ye, Alain H. Antón, Sanaz Sadeghi, Russ H. Huang, Alyosha C. Molnar

Abstract:

A high dynamic range N-path passive mixer-first receiver architecture capable of simultaneously down-converting two arbitrary bands through a single RF port is presented. The architecture consists of two passive mixers arranged in a series configuration with a transformer front-end to minimize cross-loading between mixers while still providing impedance transparency and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1541 – 1553
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3546082
Publisher: IEEE

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Device Nonideality-Aware Compute-in-Memory Array Architecting: Direct Voltage Sensing, I–V Symmetric Bitcell, and Padding Array

Device Nonideality-Aware Compute-in-Memory Array Architecting: Direct Voltage Sensing, I–V Symmetric Bitcell, and Padding Array 150 150
Author(s): Jianzi Jin, Shifan Gao, Cimang Lu, Xiang Qiu, Yi Zhao

Abstract:

A voltage sensing compute-in-memory (CIM) architecture has been designed to improve the analog computing accuracy, and a chip on 90-nm flash platform has been successfully fabricated, with the bidirectional operation enabled by the symmetric bitcell structure. By padding the weight sum to a global value for all bit lines (BLs), …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 19 – 24
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3539470
Publisher: IEEE

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Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W

Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W 150 150
Author(s): Yusaku Shiotsu, Satoshi Sugahara

Abstract:

A binarized neural-network (BNN) accelerator macro is developed based on a processing-in-memory (PIM) architecture having the ability of eight-parallel multiply-accumulate (MAC) processing. The parallel-processing PIM macro, referred to as a PPIM macro, is designed to perform the parallel processing with no use of multiport SRAM cells and to achieve the …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 25 – 33
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3538702
Publisher: IEEE

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