Computer architecture

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A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC

A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC 150 150
Author(s): Vaidehi Garg, Jianwei Jia, Omkar Phadke, Shimeng Yu

Abstract:

Compute-in-memory (CIM) using emerging nonvolatile memory devices is a promising candidate for energy-efficient deep neural network (DNN) inference at the edge. Ferroelectric field-effect transistors (FeFETs) have recently gained attention as nonvolatile, CMOS-compatible devices with a higher on/off ratio and lower read and write energy compared to resistive random-access memory (…

Published in: IEEE Solid-State Circuits Letters
Page(s): 13 – 16
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3640522
Publisher: IEEE

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A 57.3-fps 12.8 TFLOPS/W Text-to-Motion Processor With Inter-Iteration Output Sparsity and Inter-Frame Joint Similarity

A 57.3-fps 12.8 TFLOPS/W Text-to-Motion Processor With Inter-Iteration Output Sparsity and Inter-Frame Joint Similarity 150 150
Author(s): Jaehoon Heo, Adiwena Putra, Sungwoong Yune, Jieon Yoon, Hangyeol Lee, Ji-Hoon Kim, Joo-Young Kim

Abstract:

Recently, 3-D human motion generation has become essential in media applications such as film production and augmented reality (AR)/virtual reality (VR) devices, requiring the generation of human joint movements and detailed 3-D meshes for each joint. Traditionally, joint creation required hours or even days, making it impractical for real-time …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3631087
Publisher: IEEE

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A 28-nm Digital Compute-in-Memory Ising Annealer With Asynchronous Random Number Generator for Traveling Salesman Problem

A 28-nm Digital Compute-in-Memory Ising Annealer With Asynchronous Random Number Generator for Traveling Salesman Problem 150 150
Author(s): Yuyao Kong, Haomei Liu, Vaidehi Garg, Shimeng Yu

Abstract:

This work presents a compact digital compute-in-memory (DCIM) Ising annealer targeting large-scale combinatorial optimization. A centroid-based weight mapping method combined with hierarchical clustering reduces the memory capacity required for traveling salesman problem (TSP) weights, enabling efficient mapping with limited on-chip storage. An asynchronous random number generator (ARNG) based on dual …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 4
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3639178
Publisher: IEEE

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Advancing On-Cell Near-Field Monitoring for Thermal Runaway Detection in EV Batteries

Advancing On-Cell Near-Field Monitoring for Thermal Runaway Detection in EV Batteries 150 150
Author(s): Simon Foster, Scott Block, Daniel McMitchell, Edgar Colin-Beltran, Robert Dailey

Abstract:

A cell monitoring system for performance and safety enhancement is presented. It is the first commercially available single-chip-on-cell near-field contactless solution for automotive battery management, simplifying pack interconnect and reducing points of failure. This letter is a companion paper to the earlier ISSCC paper. It provides further details on the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 369 – 372
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3634340
Publisher: IEEE

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A Multicore Programmable Variable-Precision Near-Memory Accelerator for CNN and Transformer Models

A Multicore Programmable Variable-Precision Near-Memory Accelerator for CNN and Transformer Models 150 150
Author(s): Yiming Yang, Yiyang Yuan, Xinghua Wang, Xiaoran Li, Hao Wu, Qihao Liu, Weiye Tang, Xiangqu Fu, Feng Zhang

Abstract:

Convolutional neural network (CNN) and transformer are the most popular neural network models in computer vision (CV) and natural language processing (NLP). It is quite common to use both these two models in multimodal scenarios, such as text-to-image generation. However, these two models have very different memory mappings, dataflows and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3624011
Publisher: IEEE

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PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI

PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI 150 150
Author(s): Jakob Finkbeiner, Raphael Nägele, Manuel Wittlinger, Markus Grözing, Manfred Berroth, Georg Rademacher

Abstract:

Analog computing offers intrinsic energy and latency benefits that makes it attractive for real-time and edge applications. Conventional analog accelerators suffer from repeated conversions between analog and digital domain, which degrades efficiency and throughput. We propose an all-analog pipelined neural network accelerator architecture in 22 nm fully-depleted silicon-on-insulator (FD-SOI) complementary metal-oxide-semiconductor (…

Published in: IEEE Solid-State Circuits Letters
Page(s): 365 – 368
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3627274
Publisher: IEEE

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AACIM: A 2785-TOPS/W, 161-TOP/mm2, <1.17%-RMSE, Analog-In Analog-Out Computing-In-Memory Macro in 28 nm

AACIM: A 2785-TOPS/W, 161-TOP/mm2, <1.17%-RMSE, Analog-In Analog-Out Computing-In-Memory Macro in 28 nm 150 150
Author(s): Rentao Wan, Chuan-Tung Lin, Bo Zhang, Yannis Tsividis, Mingoo Seok

Abstract:

This article presents an analog-in analog-out CIM macro (AACIM) for use in analog deep neural network (DNN) processors. Our macro receives analog inputs, performs a 64-by-32 vector–matrix multiplication (VMM) with a current-discharging computation mechanism, and produces analog outputs. It stores a 4-bit weight as an analog voltage in the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3622309
Publisher: IEEE

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Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET

Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET 150 150
Author(s): Swati Deshwal, Sufia Shahin, Anirban Kar, Yogesh S. Chauhan, Hussam Amrouch

Abstract:

This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature instability (NBTI), hot carrier degradation (HCD), and the impact of back-end-of-line (BEOL) parasitics on standard cell performance. NBTI degradation is modeled using a framework …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 188 – 196
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3624653
Publisher: IEEE

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A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device

A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device 150 150
Author(s): Jen-Chun Tien, Ping-Chun Wu, Win-San Khwa, Ashwin Sanjay Lele, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang

Abstract:

The microscaling (MX) format is an emerging data representation that quantizes high-bitwidth floating-point (FP) values into low-bitwidth FP-like values with a shared-scale (SS) exponent. When implemented with computing-in-memory (CIM), MX allows an attractive tradeoff between accuracy and hardware efficiency for specific neural network (NN) workloads. This work presents the first …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3617944
Publisher: IEEE

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