compute-in-memory (CIM)

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SEAL: Multi-Tenant Security-Aware Layer Mapping for Heterogeneous 3D CiM Accelerators

SEAL: Multi-Tenant Security-Aware Layer Mapping for Heterogeneous 3D CiM Accelerators 150 150
Author(s): Pragya Sharma, Sriniketh Purisai Ramanujam, Ashish Reddy Bommana, Hossein Pourmehrani, Naghmeh Karimi, Farshad Firouzi, Krishnendu Chakrabarty

Abstract:

Heterogeneous 3D compute-in-memory (CiM) architectures have emerged as an efficient acceleration paradigm for deep neural network (DNN) inference by leveraging the complementary characteristics of diverse memory technologies enabled through 3D integration. Prior work has focused on architectural efficiency and workload-mapping optimization, leaving the security implications of heterogeneous CiM systems largely …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3734047
Publisher: IEEE

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A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI

A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI 150 150
Author(s): Jiho Chun, Byeongseon Choi, Edward Jongyoon Choi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je

Abstract:

Computing in memory (CIM) has emerged as a promising architecture that can significantly reduce power consumption and latency in edge artificial intelligence (AI) devices. For battery-constrained edge devices, non-volatile memories (NVMs) are ideal due to their ability to retain neural network parameters even when powered down, ensuring rapid response time …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3717139
Publisher: IEEE

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A 28-nm PVT Inner-Tracking Time-Domain Compute-In-Memory Macro for Edge-AI Devices

A 28-nm PVT Inner-Tracking Time-Domain Compute-In-Memory Macro for Edge-AI Devices 150 150
Author(s): Yuanzhe Zhao, Yuheng Wang, Heng Xie, Zijian Wang, Rui P. Martins, Chi-Hang Chan, Minglei Zhang

Abstract:

This article presents an energy-efficient and process-, voltage-, and temperature (PVT)-robust time-domain (TD) compute-in-memory (CIM) macro for edge artificial intelligence (AI) devices. It features: 1) a PVT inner-tracking (PIT) technique that aligns the PVT responses of TD computation and TD quantization, delivering inherent robustness without incurring extra power or circuit …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3691189
Publisher: IEEE

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Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising–Similarity for Diffusion Models

Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising–Similarity for Diffusion Models 150 150
Author(s): Ruiqi Guo, Lei Wang, Xiaofeng Chen, Keyi Jiang, Zhiheng Yue, Huiming Han, Yang Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin

Abstract:

Diffusion models have recently revolutionized the field of image synthesis due to their ability to generate photorealistic images. However, one of the main drawbacks of diffusion models is that the image generation process is expensive. Large image-to-image networks have to be applied multiple times in order to iteratively optimize the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3684745
Publisher: IEEE

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PERCEL: A Rewritable NVM CIM Incorporating a CTT-Based Per-Cell DAC

PERCEL: A Rewritable NVM CIM Incorporating a CTT-Based Per-Cell DAC 150 150
Author(s): Samyak Chakrabarty, Vinod Jacob, Mohammadreza Zeinali, Georgios Karfakis, Siyun Qiao, Ziyi Guo, Puneet Gupta, Subramanian Iyer, Sudhakar Pamarti

Abstract:

Compute-in-memory (CiM) accelerators perform matrix vector multiplications (MVMs) directly inside memory arrays, reducing data movement and improving both energy efficiency and throughput for artificial intelligence (AI) workloads. To reduce the number of conversions, recent designs use multibit compute cells. Nevertheless, practical multibit CiM still faces a tension among accuracy, efficiency, …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 70 – 77
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3680497
Publisher: IEEE

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A Folded-Differential Switched-Capacitor SRAM CIM Macro With Scalable MAC Sizes for TinyML Inference

A Folded-Differential Switched-Capacitor SRAM CIM Macro With Scalable MAC Sizes for TinyML Inference 150 150
Author(s): Zhonghao Chen, Ling-An Cheong, Tianyi Yu, Yiming Chen, Guodong Yin, Teng Yi, Yongpan Liu, Huazhong Yang, Xueqing Li

Abstract:

This letter presents a switched-capacitor SRAM compute-in-memory macro optimized for TinyML inference. Key features include: 1) an area-efficient folded-differential multiply-and-accumulate (FD-MAC) scheme to double the signal margin; 2) a closed-loop floating-inverter amplifier (FIA)-based charge accumulation technique for signal-to-noise ratio enhancement and multiply-and-accumulate (MAC) voltage integration; and 3) a sparsity-aware multistep MAC method …

Published in: IEEE Solid-State Circuits Letters
Page(s): 73 – 76
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3662477
Publisher: IEEE

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An Approximate Digital CIM Macro With Low-Power Multiply-Add Units and Dynamic Sparse-Adaptive Configuring for Edge AI Inference

An Approximate Digital CIM Macro With Low-Power Multiply-Add Units and Dynamic Sparse-Adaptive Configuring for Edge AI Inference 150 150
Author(s): Xiaofeng Li, Yi Zhan, Purui Zhu, Rui Zhou, Jiayin Song, Heng You, Yumei Zhou, Shushan Qiao

Abstract:

This letter presents an approximate digital compute-in-memory (CIM) macro for low-power edge AI inference. It introduces three hierarchical innovations: 1) novel fused approximate multiply-add units (FAMUs) that reduces power and area consumption; 2) a bit-critical weight allocation architecture that optimally balances accuracy and hardware cost; and 3) a dynamic sparsity-adaptive configuration method to …

Published in: IEEE Solid-State Circuits Letters
Page(s): 45 – 48
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3652570
Publisher: IEEE

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A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC

A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC 150 150
Author(s): Vaidehi Garg, Jianwei Jia, Omkar Phadke, Shimeng Yu

Abstract:

Compute-in-memory (CIM) using emerging nonvolatile memory devices is a promising candidate for energy-efficient deep neural network (DNN) inference at the edge. Ferroelectric field-effect transistors (FeFETs) have recently gained attention as nonvolatile, CMOS-compatible devices with a higher on/off ratio and lower read and write energy compared to resistive random-access memory (…

Published in: IEEE Solid-State Circuits Letters
Page(s): 13 – 16
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3640522
Publisher: IEEE

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DPe-CIM: A 4T-1C Dual-Port eDRAM-Based Compute-in-Memory for Simultaneous Computing and Refresh With Adaptive Refresh and Data Conversion Reduction Scheme

DPe-CIM: A 4T-1C Dual-Port eDRAM-Based Compute-in-Memory for Simultaneous Computing and Refresh With Adaptive Refresh and Data Conversion Reduction Scheme 150 150
Author(s): Do Han Kim, Minyoung Jo, Gi Seok Kim, Dong Gyun Ha, Ung Bin Oh, Donghan Ko, Jiwoo Lee, Mingu Kang, Seong-Ook Jung

Abstract:

This article presents DPe-CIM, a 4T-1C dual-port embedded dynamic random access memory (eDRAM)-based compute-in-memory (CIM) macro with adaptive refresh and data conversion reduction. DPe-CIM proposes four key features that improve area and energy efficiency: 1) dual-port eDRAM cell (DPC) separates the multiply-and-accumulate (MAC) and refresh ports, enabling simultaneous MAC …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3623117
Publisher: IEEE

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