compute-in-memory (CIM)

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SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators

SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators 150 150
Author(s): Pragya Sharma, Sriniketh Purisai Ramanujam, Ashish Reddy Bommana, Hossein Pourmehrani, Naghmeh Karimi, Farshad Firouzi, Krishnendu Chakrabarty

Abstract:

Heterogeneous 3-D compute-in-memory (CiM) architectures have emerged as an efficient acceleration paradigm for deep neural network (DNN) inference by leveraging the complementary characteristics of diverse memory technologies enabled through 3-D integration. Prior work has focused on architectural efficiency and workload-mapping optimization, leaving the security implications of heterogeneous CiM systems largely …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 205 – 213
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3734047
Publisher: IEEE

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Device–Circuit–System Co-Design of Reconfigurable Oxide–Semiconductor 2T Nonvolatile Gain-Cell Memory and Sandwich-3-D LLM Accelerator

Device–Circuit–System Co-Design of Reconfigurable Oxide–Semiconductor 2T Nonvolatile Gain-Cell Memory and Sandwich-3-D LLM Accelerator 150 150
Author(s): Luqi Zheng, Chang Niu, Shuting Du, Sumi Lee, Amir Massah Bavani, Zehao Lin, Peide D. Ye, Haitong Li

Abstract:

In this work, we present an oxide–semiconductor (OS)-based 2T nonvolatile gain-cell (NVGC) memory and a “sandwich 3-D” stacking scheme, co-designed using atomic layer deposition (ALD) InOx oxide–semiconductor FETs (OSFETs) and OS-ferroelectric FETs (FeFETs), for efficient large language model (LLM) acceleration. The new 2T-NVGC enables native, in-memory reconfiguration …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 240 – 248
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740041
Publisher: IEEE

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DRAMP: A Fully Parallel 1T1C DRAM Compute-in-Memory Macro With Mismatch-Robust Word-Line Ramp-Charging Operation

DRAMP: A Fully Parallel 1T1C DRAM Compute-in-Memory Macro With Mismatch-Robust Word-Line Ramp-Charging Operation 150 150
Author(s): Jihwan Cho, Dalta Imam Maulana, Minkyu Yang, Changjoo Park, Wanyeong Jung

Abstract:

This article presents DRAMP—the first silicon-verified, fully parallel one-transistor–one-capacitor (1T1C) dynamic random access memory (DRAM) compute-in-memory (CIM) macro for high computational density and energy efficiency. The key enabling technique is a word-line (WL) ramp-charging operation. By applying a constant-slope ramp and periodic pulses to the WLs, the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3737910
Publisher: IEEE

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An Intelligent Vision SoC With Fully Analog Sensing-to-Inference Pipeline and Linearity-Recovery RRAM Compute-in-Memory

An Intelligent Vision SoC With Fully Analog Sensing-to-Inference Pipeline and Linearity-Recovery RRAM Compute-in-Memory 150 150
Author(s): Zhengke Yang, Xiao Liu, Haofeng Yu, Zhen Kong, Humiao Li, Liang Ran, Zhichao Lu, Xinhe Feng, Liang Zhao, Yida Li, Jiamin Li, Feichi Zhou, Longyang Lin

Abstract:

Edge vision systems that integrate image sensing and neural-network inference on a single chip are constrained by inter-layer analog-to-digital converters (ADCs) and on-chip weight storage density, which together limit system efficiency and network scale. This article presents a fully analog vision system-on-chip (SoC) with 2-Mbit multi-level-cell (MLC) resistive random access …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3737258
Publisher: IEEE

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A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI

A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI 150 150
Author(s): Jiho Chun, Byeongseon Choi, Edward Jongyoon Choi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je

Abstract:

Computing in memory (CIM) has emerged as a promising architecture that can significantly reduce power consumption and latency in edge artificial intelligence (AI) devices. For battery-constrained edge devices, non-volatile memories (NVMs) are ideal due to their ability to retain neural network parameters even when powered down, ensuring rapid response time …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3717139
Publisher: IEEE

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A 28-nm PVT Inner-Tracking Time-Domain Compute-In-Memory Macro for Edge-AI Devices

A 28-nm PVT Inner-Tracking Time-Domain Compute-In-Memory Macro for Edge-AI Devices 150 150
Author(s): Yuanzhe Zhao, Yuheng Wang, Heng Xie, Zijian Wang, Rui P. Martins, Chi-Hang Chan, Minglei Zhang

Abstract:

This article presents an energy-efficient and process-, voltage-, and temperature (PVT)-robust time-domain (TD) compute-in-memory (CIM) macro for edge artificial intelligence (AI) devices. It features: 1) a PVT inner-tracking (PIT) technique that aligns the PVT responses of TD computation and TD quantization, delivering inherent robustness without incurring extra power or circuit …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3691189
Publisher: IEEE

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Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising–Similarity for Diffusion Models

Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising–Similarity for Diffusion Models 150 150
Author(s): Ruiqi Guo, Lei Wang, Xiaofeng Chen, Keyi Jiang, Zhiheng Yue, Huiming Han, Yang Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin

Abstract:

Diffusion models have recently revolutionized the field of image synthesis due to their ability to generate photorealistic images. However, one of the main drawbacks of diffusion models is that the image generation process is expensive. Large image-to-image networks have to be applied multiple times in order to iteratively optimize the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3684745
Publisher: IEEE

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PERCEL: A Rewritable NVM CIM Incorporating a CTT-Based Per-Cell DAC

PERCEL: A Rewritable NVM CIM Incorporating a CTT-Based Per-Cell DAC 150 150
Author(s): Samyak Chakrabarty, Vinod Jacob, Mohammadreza Zeinali, Georgios Karfakis, Siyun Qiao, Ziyi Guo, Puneet Gupta, Subramanian Iyer, Sudhakar Pamarti

Abstract:

Compute-in-memory (CiM) accelerators perform matrix vector multiplications (MVMs) directly inside memory arrays, reducing data movement and improving both energy efficiency and throughput for artificial intelligence (AI) workloads. To reduce the number of conversions, recent designs use multibit compute cells. Nevertheless, practical multibit CiM still faces a tension among accuracy, efficiency, …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 70 – 77
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3680497
Publisher: IEEE

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A Folded-Differential Switched-Capacitor SRAM CIM Macro With Scalable MAC Sizes for TinyML Inference

A Folded-Differential Switched-Capacitor SRAM CIM Macro With Scalable MAC Sizes for TinyML Inference 150 150
Author(s): Zhonghao Chen, Ling-An Cheong, Tianyi Yu, Yiming Chen, Guodong Yin, Teng Yi, Yongpan Liu, Huazhong Yang, Xueqing Li

Abstract:

This letter presents a switched-capacitor SRAM compute-in-memory macro optimized for TinyML inference. Key features include: 1) an area-efficient folded-differential multiply-and-accumulate (FD-MAC) scheme to double the signal margin; 2) a closed-loop floating-inverter amplifier (FIA)-based charge accumulation technique for signal-to-noise ratio enhancement and multiply-and-accumulate (MAC) voltage integration; and 3) a sparsity-aware multistep MAC method …

Published in: IEEE Solid-State Circuits Letters
Page(s): 73 – 76
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3662477
Publisher: IEEE

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