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A CMOS LNA With an Integrated Direct-Conversion Mixer-Based Power Detector for Low-Power IoT Radio Applications

A CMOS LNA With an Integrated Direct-Conversion Mixer-Based Power Detector for Low-Power IoT Radio Applications 150 150
Author(s): Yunfan Gao, Minghan Liu, Mengting Yan, Cristian Cassella, Miriam Leeser, Marvin Onabajo

Abstract:

This letter presents a 2.8-GHz low-power CMOS low-noise amplifier (LNA) with an embedded self-mixing power detector (PD) for low-overhead RF power monitoring. The detector reuses two existing LNA node voltages as the signal and local oscillator (LO) inputs for direct downconversion mixing, which avoids a dedicated LO generator, coupler, or …

Published in: IEEE Solid-State Circuits Letters
Page(s): 258 – 261
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3725828
Publisher: IEEE

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A Delay-Compensated RC Oscillator With Constant Ramp Peak-Voltage Achieving 23 ppm/°C Temperature Coefficient from -40 to 100 °C

A Delay-Compensated RC Oscillator With Constant Ramp Peak-Voltage Achieving 23 ppm/°C Temperature Coefficient from -40 to 100 °C 150 150
Author(s): Wenbo Zhang, Fantao Wang, Junyi Liu, Yanzhao Ma

Abstract:

This letter presents a delay-compensated RC relaxation oscillator for enhanced frequency stability. The proposed architecture employs a peak-sampling circuit to detect the charging-capacitor peak voltage. A feedback loop composed of an error amplifier and compensation resistors adaptively raises the capacitor DC baseline to compensate for comparator-delay-induced frequency error, while phase-alternating …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3738818
Publisher: IEEE

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Device–Circuit–System Co-Design of Reconfigurable Oxide–Semiconductor 2T Nonvolatile Gain-Cell Memory and Sandwich-3-D LLM Accelerator

Device–Circuit–System Co-Design of Reconfigurable Oxide–Semiconductor 2T Nonvolatile Gain-Cell Memory and Sandwich-3-D LLM Accelerator 150 150
Author(s): Luqi Zheng, Chang Niu, Shuting Du, Sumi Lee, Amir Massah Bavani, Zehao Lin, Peide D. Ye, Haitong Li

Abstract:

In this work, we present an oxide–semiconductor (OS)-based 2T nonvolatile gain-cell (NVGC) memory and a “sandwich 3-D” stacking scheme, co-designed using atomic layer deposition (ALD) InOx oxide–semiconductor FETs (OSFETs) and OS-ferroelectric FETs (FeFETs), for efficient large language model (LLM) acceleration. The new 2T-NVGC enables native, in-memory reconfiguration …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 240 – 248
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740041
Publisher: IEEE

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A Threshold-Voltage Self-Compensated Dual-Gate IGZO TFT Cell for Robust In-Sensor Computing

A Threshold-Voltage Self-Compensated Dual-Gate IGZO TFT Cell for Robust In-Sensor Computing 150 150
Author(s): Zhi Li, Zikang Mei, Wei Tang

Abstract:

In-sensor computing (ISC) based on amorphous metal-oxide thin-film transistors (TFTs) promises compact, high-density vision chips, yet large-scale integration is vulnerable to process-induced threshold-voltage ( $V_{th}$ ) variations that critically degrade computational robustness and accuracy. This work proposes a novel 3T1C (3-Transistor, 1-Capacitor) ISC cell circuit based on photodiode (PD)-gated …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 214 – 222
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3736074
Publisher: IEEE

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Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile 1-bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference

Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile 1-bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference 150 150
Author(s): Byeong-Gwon Kim, Byeong-Kwon Ju, Ki-Young Lee

Abstract:

The spin-transfer-torque magnetic random access memory (STT-MRAM) is attractive for nonvolatile 1-bit sign-weight storage, but a favorable cell or local-read metric does not establish subsystem efficiency. We analyze a hybrid magnetic tunnel junction (MTJ)–complementary metal–oxide–semiconductor (CMOS) memory subsystem, in which MTJs store static signs while sensing, reference …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 192 – 198
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3726699
Publisher: IEEE

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Probabilistic Computing With Neuromorphic Elements

Probabilistic Computing With Neuromorphic Elements 150 150
Author(s): Zonglong Li, Laurie E. Calvet

Abstract:

This article presents a compact and low-power approach to probabilistic inference based on time-domain analog computation. The proposed system implements a Bayesian classifier using neuromorphic circuit elements simulated in a 130-nm CMOS technology. Probabilities are encoded in the duty cycle of deterministic spiking signals generated by neuron circuits, while likelihood …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 167 – 175
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3712198
Publisher: IEEE

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Self-Heating and Parasitic Effects in Multi-Tier CFET Design

Self-Heating and Parasitic Effects in Multi-Tier CFET Design 150 150
Author(s): Sufia Shahin, Mahdi Benkhelifa, Yogesh Singh Chauhan, Hussam Amrouch

Abstract:

In this article, we study the impact of self-heating effects (SHEs) and middle of line (MOL) and back-end of line (BEOL) induced parasitics on multi-tier CFET design, where multiple nanosheet devices are vertically stacked. We analyze and compare the four-tier complementary FET (CFET) design with the conventional two-tier CFET, using …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 153 – 158
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704373
Publisher: IEEE

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A 256-Channel Solid-State Nanopore Readout Array With 193-pA TIAs and Event Detection at 1-MHz in 65-nm CMOS

A 256-Channel Solid-State Nanopore Readout Array With 193-pA TIAs and Event Detection at 1-MHz in 65-nm CMOS 150 150
Author(s): Sander Crols, Filip Tavernier, Carolina Mora Lopez, Marian Verhelst, Nick Van Helleputte

Abstract:

Solid-state nanopore single-molecule sensing aims to replace the commercially available biological nanopores. Array sizes have remained limited due to the area and power consumption of the transimpedance amplifiers (TIAs), thus preventing throughput and cost scaling. This article presents a 256-channel readout array for solid-state nanopore single-molecule sensing in 65 nm CMOS. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721767
Publisher: IEEE

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A 10-bit Source-Driver IC for High-Resolution OLED-on-Silicon Displays With All-Channel Automatic Offset Calibration and Data-Aware Slew-Rate Enhancement

A 10-bit Source-Driver IC for High-Resolution OLED-on-Silicon Displays With All-Channel Automatic Offset Calibration and Data-Aware Slew-Rate Enhancement 150 150
Author(s): Junghwan Oh, Wiman Yoo, Dong-Kun Lee, Dong-Hyun Kim, Jong-Seok Kim

Abstract:

This article presents a 10-bit source-driver (SD) IC for high-resolution OLED-on-silicon (OLEDoS) microdisplays in augmented reality (AR)/virtual reality (VR) applications. To address the stringent constraints of aggressive area scaling, sub-microsecond settling time, and high output uniformity, three key techniques are proposed. First, a demultiplexer (DEMUX)-based channel width expansion …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3726042
Publisher: IEEE

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