Capacitors

A 28-nm 18.7 TOPS/mm $^2$ 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh

A 28-nm 18.7 TOPS/mm $^2$ 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh 150 150

Abstract:

This article reports a high-density 3T1C single-finger (SF) embedded dynamic random access memory (eDRAM) compute-in-memory (CIM) macro. It features several techniques that enhance the memory density, the energy efficiency, and the throughput density, namely: 1) a high-density 3T1C SF-eDRAM cell with low-leakage retention (LLR) to improve the memory density …

View on IEEE Xplore

A Ten-Level Series-Capacitor 24-to-1-V DC–DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node Power Rail

A Ten-Level Series-Capacitor 24-to-1-V DC–DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node Power Rail 150 150

Abstract:

This work presents a high-efficiency ten-level series-capacitor 24-to-1-V buck converter with three techniques to improve its efficiency and reliability. First, we propose a fast in situ efficiency tracking (FIT) technique to maximize efficiency across load conditions and process, voltage, and temperature (PVT) variations. The second technique is the power-FET …

View on IEEE Xplore

A High-Efficiency Low-Cost Multi-Antenna Energy Harvesting System With Leakage Suppression

A High-Efficiency Low-Cost Multi-Antenna Energy Harvesting System With Leakage Suppression 150 150

Abstract:

This article presents a multi-antenna RF energy harvester (MARFEH) with leakage suppression to achieve high output power and avoid the effects of interference and blind spots in the room, and all the RF rectifiers share only one buffering capacitor to achieve low cost. The proposed leakage-suppressed rectifier utilizing adaptive $V_{…

View on IEEE Xplore

A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse

A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse 150 150

Abstract:

The design and measurement of a time-domain analog spiking neuron is described. The proposed neuron leverages time-domain processing using voltage-controlled oscillators (VCOs) and a time-domain comparator to integrate the input spike and trigger the output spike. A novel leaky circuit uses a phase-locked loop (PLL) to drive the phase difference …

View on IEEE Xplore

Corrections to “A Synchronized Switch Harvesting Rectifier With Reusable Storage Capacitors for Piezoelectric Energy Harvesting”

Corrections to “A Synchronized Switch Harvesting Rectifier With Reusable Storage Capacitors for Piezoelectric Energy Harvesting” 150 150

Abstract:

In the above article [1], page 2605, the changes in Table II are as follows.

View on IEEE Xplore

A 2.8 $\mu$ s Response Time 95.1% Efficiency Hybrid Boost Converter With RHP Zero Elimination for Fast-Transient Applications

A 2.8 $\mu$ s Response Time 95.1% Efficiency Hybrid Boost Converter With RHP Zero Elimination for Fast-Transient Applications 150 150

Abstract:

This article proposes a hybrid boost converter that eliminates the right-half-plane (RHP) zero. The proposed converter can be designed with a broad bandwidth up to a tenth of the switching frequency, such that the converter can attain fast transient response as a buck converter. Besides, it features a left-half-plane zero …

View on IEEE Xplore

A 50–67-GHz Transformer-Based Six-Port Balanced-to-Unbalanced Quadrature Hybrid Coupler

A 50–67-GHz Transformer-Based Six-Port Balanced-to-Unbalanced Quadrature Hybrid Coupler 150 150

Abstract:

This letter presents the first on-chip transformer-based six-port balanced-to-unbalanced quadrature hybrid coupler (QHBC). The proposed six-port QHBC employs three transformers to replace eight inductors design in conventional LC-based couplers for miniaturization. Fabricated in CMOS 28 nm, the overall size of the proposed coupler is 0.23 mm $\times0.17$ mm, which is equivalent to $0.046\…

View on IEEE Xplore

An Ultrasound Receiver With Bandwidth-Enhanced Current Conveyor and Element-Level Ultrasound Transmitter for Ultrasound Imaging Systems

An Ultrasound Receiver With Bandwidth-Enhanced Current Conveyor and Element-Level Ultrasound Transmitter for Ultrasound Imaging Systems 150 150

Abstract:

In this letter, we present an ultrasound (US) imaging system with a low-noise US receiver (RX) and an element-level US transmitter (TX) for a capacitive micromachined ultrasonic transducer (CMUT). The proposed US RX isolates the input parasitic capacitance $(C_{P})$ from the front-end transimpedance stage by using a bandwidth-enhanced current …

View on IEEE Xplore

A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array

A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array 150 150

Abstract:

Analog computing-in-memory (CIM) using emerging resistive nonvolatile memory (NVM) technologies faces challenges, such as static power consumption, current flow-induced IR drop, and the need for multiple power-hungry ADCs. In this letter, we present ferroelectric capacitive array (FCA)-based energy/area-efficient CIM macro used for charge-domain multiply-and-accumulate operations, which addresses the …

View on IEEE Xplore