Augmented reality (AR)

  • No Comments

A 28-nm CMOS 1-Chip In-Pixel Memory Backplane Circuit for 1800 × 1350 6652-PPI MicroLED AR Glasses With Per-Pixel Current Sensing and Compensation

A 28-nm CMOS 1-Chip In-Pixel Memory Backplane Circuit for 1800 × 1350 6652-PPI MicroLED AR Glasses With Per-Pixel Current Sensing and Compensation 150 150
Author(s): Sunkwon Kim, Yongil Kwon, Youngkil Choi, Taehyun Kwon, Seongyoung Ryu, Sewhan Na, Kangjoo Kim, Uijong Song, Heejin Lee, Hyun-Wook Lim, Jongwoo Lee, Jae-Youl Lee

Abstract:

This article presents a 28-nm CMOS 1-chip LED-on-Silicon (LEDoS) backplane (BP) for 6652-pixel-per-inch (PPI) microLED ( $mu $ LED) augmented reality (AR) displays. To address power and display quality challenges in AR glasses, the proposed BP employs two low-power techniques: self-refresh and partial update, and introduces four display quality enhancement methods: MSB …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3737236
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 10-bit Source-Driver IC for High-Resolution OLED-on-Silicon Displays With All-Channel Automatic Offset Calibration and Data-Aware Slew-Rate Enhancement

A 10-bit Source-Driver IC for High-Resolution OLED-on-Silicon Displays With All-Channel Automatic Offset Calibration and Data-Aware Slew-Rate Enhancement 150 150
Author(s): Junghwan Oh, Wiman Yoo, Dong-Kun Lee, Dong-Hyun Kim, Jong-Seok Kim

Abstract:

This article presents a 10-bit source-driver (SD) IC for high-resolution OLED-on-silicon (OLEDoS) microdisplays in augmented reality (AR)/virtual reality (VR) applications. To address the stringent constraints of aggressive area scaling, sub-microsecond settling time, and high output uniformity, three key techniques are proposed. First, a demultiplexer (DEMUX)-based channel width expansion …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3726042
Publisher: IEEE

View on IEEE Xplore

  • No Comments

IRIS: An Energy-Efficient Spatial Computing SoC for Real-Time Interactive Rendering and Modeling With Surface-Aware 3-D Gaussian Splatting

IRIS: An Energy-Efficient Spatial Computing SoC for Real-Time Interactive Rendering and Modeling With Surface-Aware 3-D Gaussian Splatting 150 150
Author(s): Seokchan Song, Seryeong Kim, Wonhoon Park, Jongjun Park, Sanghyuk An, Gwangtae Park, Minseo Kim, Hoi-Jun Yoo

Abstract:

The 3-D Gaussian splatting (3DGS), based on a machine learning-driven radiance field technique, is rapidly emerging as a next-generation solution in 3-D graphics. Owing to its short modeling time, computational simplicity, and high rendering quality, it is expected to replace traditional 3-D graphics on edge devices. However, its substantial memory …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3613707
Publisher: IEEE

View on IEEE Xplore

Search this website