Artificial neural networks

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A 0.8μm 32Mpixel Always-On CMOS Image Sensor With Windmill-Pattern Edge Extraction and On-Chip DNN

A 0.8μm 32Mpixel Always-On CMOS Image Sensor With Windmill-Pattern Edge Extraction and On-Chip DNN 150 150
Author(s): Mamoru Sato, Sachio Akebono, Kazuyoshi Yasuoka, Eriko Kato, Masahiro Tsuruta, Chiaki Takano, Kensuke Ota, Kazuki Haraguchi, Masahiro Watanabe, Genki Fujii, Koichiro Yamanaka, Kazunori Yasuda, Satoshi Minami, Katsuhiko Hanzawa, Kohei Matsuda, Akihiko Kato, Yosuke Ueno

Abstract:

This paper presents a CMOS image sensor (CIS) that integrates two operation modes: a high-resolution viewing mode with 0.8μm 32 Mpixels and a low-power always-on object recognition mode consuming 2.67 mW at 10 fps. The CIS features a unique windmill-pattern analog edge extraction circuit that is resilient to illumination variations. An on-chip deep …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3628314
Publisher: IEEE

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PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI

PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI 150 150
Author(s): Jakob Finkbeiner, Raphael Nägele, Manuel Wittlinger, Markus Grözing, Manfred Berroth, Georg Rademacher

Abstract:

Analog computing offers intrinsic energy and latency benefits that makes it attractive for real-time and edge applications. Conventional analog accelerators suffer from repeated conversions between analog and digital domain, which degrades efficiency and throughput. We propose an all-analog pipelined neural network accelerator architecture in 22 nm FD-SOI CMOS. Measurements of a …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3627274
Publisher: IEEE

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AACIM: A 2785-TOPS/W, 161-TOP/mm2, <1.17%-RMSE, Analog-In Analog-Out Computing-In-Memory Macro in 28 nm

AACIM: A 2785-TOPS/W, 161-TOP/mm2, <1.17%-RMSE, Analog-In Analog-Out Computing-In-Memory Macro in 28 nm 150 150
Author(s): Rentao Wan, Chuan-Tung Lin, Bo Zhang, Yannis Tsividis, Mingoo Seok

Abstract:

This article presents an analog-in analog-out CIM macro (AACIM) for use in analog deep neural network (DNN) processors. Our macro receives analog inputs, performs a 64-by-32 vector–matrix multiplication (VMM) with a current-discharging computation mechanism, and produces analog outputs. It stores a 4-bit weight as an analog voltage in the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3622309
Publisher: IEEE

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A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device

A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device 150 150
Author(s): Jen-Chun Tien, Ping-Chun Wu, Win-San Khwa, Ashwin Sanjay Lele, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang

Abstract:

The microscaling (MX) format is an emerging data representation that quantizes high-bitwidth floating-point (FP) values into low-bitwidth FP-like values with a shared-scale (SS) exponent. When implemented with computing-in-memory (CIM), MX allows an attractive tradeoff between accuracy and hardware efficiency for specific neural network (NN) workloads. This work presents the first …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3617944
Publisher: IEEE

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A 28-nm Computing-in-Memory Processor With Zig-Zag Backbone-Systolic CIM and Block-/Self-Gating CAM for NN/Recommendation Applications

A 28-nm Computing-in-Memory Processor With Zig-Zag Backbone-Systolic CIM and Block-/Self-Gating CAM for NN/Recommendation Applications 150 150
Author(s): Shengzhe Yan, Zhuoyu Dai, Zhaori Cong, Zeyu Guo, Yifan He, Wenyu Sun, Chunmeng Dou, Feng Zhang, Jinshan Yue, Yongpan Liu, Ming Liu

Abstract:

Computing-in-memory (CIM) chips have demonstrated promising energy efficiency for artificial intelligence (AI) applications such as neural networks (NNs), Transformer, and recommendation system (RecSys). However, several challenges still exist. First, a large gap between the macro and system-level CIM energy efficiency is observed. Second, several memory-dominate operations, such as embedding in …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3610539
Publisher: IEEE

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ROZK: An Energy-Efficient DNN Accelerator Based on Reconfigurable NoC and Local Zero-Skipping

ROZK: An Energy-Efficient DNN Accelerator Based on Reconfigurable NoC and Local Zero-Skipping 150 150
Author(s): Heetak Kim, Yunpyo Hong, Byungsoo Kim, Jongsun Park

Abstract:

Zero-skipping is a famous technique to improve the energy efficiency of deep neural network (DNN) accelerators. When the zero-skipping is realized with encoded data using lossless compression, irregular and unpredictable size of data due to inconsistent compression rate incurs several design issues including: 1) load imbalance from irregularity of data stored …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3604814
Publisher: IEEE

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Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W

Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W 150 150
Author(s): Yusaku Shiotsu, Satoshi Sugahara

Abstract:

A binarized neural-network (BNN) accelerator macro is developed based on a processing-in-memory (PIM) architecture having the ability of eight-parallel multiply-accumulate (MAC) processing. The parallel-processing PIM macro, referred to as a PPIM macro, is designed to perform the parallel processing with no use of multiport SRAM cells and to achieve the …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 25 – 33
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3538702
Publisher: IEEE

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