Accuracy

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A Zero-Voltage Switching Buck Converter With Enhanced Efficiency Over a Wide Load Range

A Zero-Voltage Switching Buck Converter With Enhanced Efficiency Over a Wide Load Range 150 150
Author(s): Jingyi Yuan, Qingqing Min, Siyang Liu, Lin Cheng

Abstract:

This article presents a wide-input-range buck converter featuring a conduction-loss-minimized zero-voltage switching (ZVS) technique. The proposed ZVS topology enables accurate ZVS operation across a wide range of input voltage ( $V_{\mathrm {IN}}$ ) and load current ( $I_{\mathrm {O}}$ ). By keeping the auxiliary inductor current pulse in the ZVS branch separate …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3609411
Publisher: IEEE

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An 8.62-μW 75-dB DRSoC Fully Integrated SoC for Spoken Language Understanding

An 8.62-μW 75-dB DRSoC Fully Integrated SoC for Spoken Language Understanding 150 150
Author(s): Sheng Zhou, Zixiao Li, Longbiao Cheng, Jérôme Hadorn, Chang Gao, Qinyu Chen, Tobi Delbruck, Kwantae Kim, Shih-Chii Liu

Abstract:

We present a sub-10- $\mu $ W fully integrated SoC for on-device spoken language understanding (SLU). Its analog feature extractor (FEx) applies global and per-channel automatic gain control (AGC) to extend the system’s dynamic range (DR)—a critical requirement for real-world scenarios, including far-field operations. The on-chip streaming-mode recurrent …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3602936
Publisher: IEEE

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LIF Neuron Based on a Charge-Powered Ring Oscillator in Weak Inversion Achieving 201 fJ/SOP

LIF Neuron Based on a Charge-Powered Ring Oscillator in Weak Inversion Achieving 201 fJ/SOP 150 150
Author(s): Javier Granizo, Ruben Garvi, Ricardo Carrero, Luis Hernandez

Abstract:

This letter presents the experimental results of a leaky-integrate-and-fire neuron (LIF) neuron based on time-domain analog circuitry. This kind of neuron is the core of spiking neural network (SNN) used in edge applications. Edge applications require power-efficient neuron designs whose power consumption is extremely low when idle, and low when …

Published in: IEEE Solid-State Circuits Letters
Page(s): 249 – 252
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3603335
Publisher: IEEE

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MIX-ACIM: A 28-nm Mixed-Precision Analog Compute-in-Memory With Digital Feature Restoration for Vector-Matrix Multiplication

MIX-ACIM: A 28-nm Mixed-Precision Analog Compute-in-Memory With Digital Feature Restoration for Vector-Matrix Multiplication 150 150
Author(s): Wei-Chun Wang, Shida Zhang, Laith Shamieh, Narasimha Vasishta Kidambi, Isha Chakraborty, Saibal Mukhopadhyay

Abstract:

A mixed-precision analog compute-in-memory (Mix-ACIM) is presented for mixed-precision vector-matrix multiplication (VMM). The design features an all-analog current-domain fixed-point (FxP) VMM with floating-point conversion and feature restoration. A 28 nm CMOS test chip shows 41 TOPS/W and 24 TOPS/mm2 for FxP (8-bit input/weight and 12-bit output) and 24.18 TFLOPS/W and 3.3 …

Published in: IEEE Solid-State Circuits Letters
Page(s): 213 – 216
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3590757
Publisher: IEEE

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MINOTAUR: A Posit-Based 0.42–0.50-TOPS/W Edge Transformer Inference and Training Accelerator

MINOTAUR: A Posit-Based 0.42–0.50-TOPS/W Edge Transformer Inference and Training Accelerator 150 150
Author(s): Kartik Prabhu, Robert M. Radway, Jeffrey Yu, Kai Bartolone, Massimo Giordano, Fabian Peddinghaus, Yonatan Urman, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina

Abstract:

Transformer models have revolutionized natural language processing (NLP) and enabled many new applications, but are challenging to deploy on resource-constrained edge devices due to their high computation and memory demands. We present MINOTAUR, an edge system-on-chip (SoC) for inference and fine-tuning of Transformer models with all memory on the chip. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1311 – 1323
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3545731
Publisher: IEEE

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Device Nonideality-Aware Compute-in-Memory Array Architecting: Direct Voltage Sensing, I–V Symmetric Bitcell, and Padding Array

Device Nonideality-Aware Compute-in-Memory Array Architecting: Direct Voltage Sensing, I–V Symmetric Bitcell, and Padding Array 150 150
Author(s): Jianzi Jin, Shifan Gao, Cimang Lu, Xiang Qiu, Yi Zhao

Abstract:

A voltage sensing compute-in-memory (CIM) architecture has been designed to improve the analog computing accuracy, and a chip on 90-nm flash platform has been successfully fabricated, with the bidirectional operation enabled by the symmetric bitcell structure. By padding the weight sum to a global value for all bit lines (BLs), …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 19 – 24
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3539470
Publisher: IEEE

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