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A Multi-Event, 7.9-ps Resolution Time Amplification-Based TDC With an Ultra-Low Static Phase Error DLL Using Interpolator Recycling Technique for dToF Applications

A Multi-Event, 7.9-ps Resolution Time Amplification-Based TDC With an Ultra-Low Static Phase Error DLL Using Interpolator Recycling Technique for dToF Applications 150 150

Abstract:

In this article, a multi-event time-to-digital converter (TDC) with a high conversion rate using an interpolator recycling technique is proposed. The conversion dead time is greatly reduced by reusing the coarse interpolation channel (CIC) during the quantization of Start and Stop signals. A high resolution is achieved by a coarse–…

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A Photovoltaic Dynamic Vision Sensor

A Photovoltaic Dynamic Vision Sensor 150 150

Abstract:

This article reports a dynamic vision sensor (DVS) proof-of-concept chip employing an unconventional photo-transduction front end. Instead of the conventional logarithmic transducer comprising a photodiode and a nonlinear load, the proposed pixel architecture uses a single diode operating in the photovoltaic regime. This operation regime, the same as employed for …

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Design of a Compact, Highly Efficient, and High-Power Q-/V-Band SiGe HBT Cascode Power Amplifier With a Four-Way Wilkinson Power Combiner Balun

Design of a Compact, Highly Efficient, and High-Power Q-/V-Band SiGe HBT Cascode Power Amplifier With a Four-Way Wilkinson Power Combiner Balun 150 150

Abstract:

This article presents a compact, efficient, and linear Q-/V-band silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) cascode power amplifier (PA) for emerging very low-Earth-orbit (VLEO) satellite communication (SATCOM). A novel four-way Wilkinson combiner balun (WCB), realized by two coupled line impedance inverting baluns (ZIBs) and isolation (ISO) resistors ( $R_{…

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A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power

A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power 150 150

Abstract:

Conventional low-voltage (LV) static random access memories (SRAMs) utilizing separate read-and-write assist circuits sacrifice access speed too much, leading to poor energy efficiency. Overlaying additional assist circuits to enable power-saving modes can exacerbate speed loss and energy inefficiency. This work proposes a coordinated read-write-hold-retention-shutdown (SD) assist circuit design for SRAMs …

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A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power

A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power 150 150

Abstract:

Conventional low-voltage (LV) static random access memories (SRAMs) utilizing separate read-and-write assist circuits sacrifice access speed too much, leading to poor energy efficiency. Overlaying additional assist circuits to enable power-saving modes can exacerbate speed loss and energy inefficiency. This work proposes a coordinated read-write-hold-retention-shutdown (SD) assist circuit design for SRAMs …

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A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power

A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power 150 150

Abstract:

Conventional low-voltage (LV) static random access memories (SRAMs) utilizing separate read-and-write assist circuits sacrifice access speed too much, leading to poor energy efficiency. Overlaying additional assist circuits to enable power-saving modes can exacerbate speed loss and energy inefficiency. This work proposes a coordinated read-write-hold-retention-shutdown (SD) assist circuit design for SRAMs …

View on IEEE Xplore

A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power

A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power 150 150

Abstract:

Conventional low-voltage (LV) static random access memories (SRAMs) utilizing separate read-and-write assist circuits sacrifice access speed too much, leading to poor energy efficiency. Overlaying additional assist circuits to enable power-saving modes can exacerbate speed loss and energy inefficiency. This work proposes a coordinated read-write-hold-retention-shutdown (SD) assist circuit design for SRAMs …

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A 10-Gb/s Optical Receiver With Monolithically Integrated PIN Photodiode, Novel AGC, and Sensitivity of –27.1 dBm for BER 10-3

A 10-Gb/s Optical Receiver With Monolithically Integrated PIN Photodiode, Novel AGC, and Sensitivity of –27.1 dBm for BER 10-3 150 150

Abstract:

A monolithically integrated optical receiver in InP for 10-Gb/s intensity modulation direct detect (IMDD) application is presented. The sensitivity at the bit error rate (BER) $rm 10^{-3}$ is measured to be –27.1 dBm. An integrated PIN diode photodetector (PD) minimizes the parasitics caused by wire bonds between the PD and …

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A 10-Gb/s Optical Receiver With Monolithically Integrated PIN Photodiode, Novel AGC, and Sensitivity of –27.1 dBm for BER 10-3

A 10-Gb/s Optical Receiver With Monolithically Integrated PIN Photodiode, Novel AGC, and Sensitivity of –27.1 dBm for BER 10-3 150 150

Abstract:

A monolithically integrated optical receiver in InP for 10-Gb/s intensity modulation direct detect (IMDD) application is presented. The sensitivity at the bit error rate (BER) $rm 10^{-3}$ is measured to be –27.1 dBm. An integrated PIN diode photodetector (PD) minimizes the parasitics caused by wire bonds between the PD and …

View on IEEE Xplore