A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power

Abstract:

Conventional low-voltage (LV) static random access memories (SRAMs) utilizing separate read-and-write assist circuits sacrifice access speed too much, leading to poor energy efficiency. Overlaying additional assist circuits to enable power-saving modes can exacerbate speed loss and energy inefficiency. This work proposes a coordinated read-write-hold-retention-shutdown (SD) assist circuit design for SRAMs …