IEEE Solid-State Circuits Letters – Early Access

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Minimizing the Noise in Low-Current Sensing by MOSFET PN-Junction Diode Feedback

Minimizing the Noise in Low-Current Sensing by MOSFET PN-Junction Diode Feedback 150 150
Author(s): Ehsan Semsar Parapari, Marco Bennati, Michele Biondi, Marco Crescentini, Federico Thei

Abstract:

This letter proposes a transimpedance amplifier (TIA) architecture that minimizes noise for continuous-time (CT) low-current sensing. The approach leverages a MOSFET to realize a pure PN-junction diode as the TIA feedback element, such that MOS channel conduction is completely suppressed. Therefore, channel-induced noise contributions associated with conventional MOS-based feedback TIAs …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3692971
Publisher: IEEE

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A 60-GHz Class-F2,3 Standing-wave Oscillator Employing Triple-line Resonator Achieving -189 dBc/Hz FoM in 65-nm CMOS

A 60-GHz Class-F2,3 Standing-wave Oscillator Employing Triple-line Resonator Achieving -189 dBc/Hz FoM in 65-nm CMOS 150 150
Author(s): Wei-Yu Lin, Nikhil Jain, Jun-Chau Chien

Abstract:

Implementing oscillators with harmonic engineering beyond 60 GHz poses significant challenges due to the need for small inductors resonating beyond 120 GHz. To address this issue, this work presents a 60-GHz standing-wave oscillator with both 2nd and 3rd-harmonic boosting for phase noise reduction. A triple-line resonator is proposed to sustain both fundamental …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3693153
Publisher: IEEE

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FeFET-Based CMOS Current Starvation Programmable Delay Element

FeFET-Based CMOS Current Starvation Programmable Delay Element 150 150
Author(s): Albi Mema, Simon Thomann, Hussam Amrouch

Abstract:

Programmable delay elements (PDEs) are crucial circuit building blocks that enable precise timing adjustments of signal transitions. They are used in various critical applications, like time-to-digital converters. They are often used to mitigate aging by clock skew tuning post-fabrication. However, typical CMOS PDE designs require many transistors while still offering …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3692304
Publisher: IEEE

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A 256-Element Slepian Beamforming Accelerator with Analog Compute-In-Memory Multiplication and Accumulation

A 256-Element Slepian Beamforming Accelerator with Analog Compute-In-Memory Multiplication and Accumulation 150 150
Author(s): Wei-Chun Wang, Shida Zhang, Coleman DeLude, Laith Shamieh, Nael Mizanur Rahman, Isha Chakraborty, Justin Romberg, Saibal Mukhopadhyay

Abstract:

An analog compute-in-memory Slepian beamforming accelerator is introduced for large-scale MIMO. The design performs complex-valued vector–matrix multiplication in the analog domain to project 256 I/Q inputs into a low-dimensional Slepian subspace and uses a digital backend with 4-tap FIR filters to generate one output beam. A test chip fabricated …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3690381
Publisher: IEEE

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A 0.015-mm2 0.5-V Synthesizable Hybrid PLL With Multi-Phase Linear Proportional-Gain Paths

A 0.015-mm2 0.5-V Synthesizable Hybrid PLL With Multi-Phase Linear Proportional-Gain Paths 150 150
Author(s): Qibang Sun, Liqun Feng, Woogeun Rhee, Hanjun Jiang

Abstract:

This brief presents a 0.015-mm2 0.5-V synthesizable hybrid phase locked loop (PLL). All blocks including an analog proportional-gain path can be logically or physically synthesized with digital cells and hardware languages. To mitigate the mismatch and common-mode fluctuation problems of a voltage-mode phase detector, multi-phase proportional-gain paths are designed for …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3649215
Publisher: IEEE

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A Fully-Dynamic Capacitive Touch Sensor With Tri-level Energy Recycling and Compressive Sensing Technique

A Fully-Dynamic Capacitive Touch Sensor With Tri-level Energy Recycling and Compressive Sensing Technique 150 150
Author(s): Xiangdong Feng, Zhiyu Wang, Haoyang Li, Jiaqing Li, Wei-Chin Lin, Xin Hu, Zhong Tang, Yuyan Liu, Qinwen Fan, Yuxuan Luo, Bo Zhao

Abstract:

Capacitive touch screens have become the dominant user interface over the past decade. Achieving high framerates with low power consumption remains a critical design goal for touch systems. The conventional charge-recycling technique reduces driving power by 64%, but it relies on off-chip capacitors. To address this issue, we propose a tri-level …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3612093
Publisher: IEEE

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A 2 pA/ √Hz Input-Referred Noise TIA in 180-nm CMOS With 2.5GHz Bandwidth for Optical Receiver

A 2 pA/ √Hz Input-Referred Noise TIA in 180-nm CMOS With 2.5GHz Bandwidth for Optical Receiver 150 150
Author(s): Yihao Yang, Dan Li, Nan Qi, Binhao Wang

Abstract:

This letter describes an ultra-low-noise, high-speed transimpedance amplifier (TIA) applied to the analog front-end (AFE) circuit of the high-sensitivity optical receiver. A combination of a three-stage amplifier and two positive feedback Miller capacitors is introduced to comprehensively reduce the input-referred noise current (IRNC) of a shunt-feedback TIA (SFTIA) and to …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3584266
Publisher: IEEE

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A 10.9nV/√Hz, 74.9dB-DR, 20MS/s Ultrasound Analog Front End for Fully-Digital Beamforming

A 10.9nV/√Hz, 74.9dB-DR, 20MS/s Ultrasound Analog Front End for Fully-Digital Beamforming 150 150
Author(s): Changde Ding, Yan Zhu, Pengjie Wang, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents a compact and energy-efficient analog front-end (AFE) circuit for fully-digital beamforming in endoscopic and catheter-based 3D-ultrasound imaging. The AFE converts single-ended analog input from each transducer element into a 10-bit digital output through a low-noise amplifier (LNA) and a 20 MS/s SAR ADC. To minimize chip area …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3581584
Publisher: IEEE

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Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency

Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency 150 150
Author(s): Yichen Xu, Zhaoqing Wang, Rentao Wan, Suhwan Kim, Minxiang Gong, Ram Krishnamurthy, Xin Zhang, Mingoo Seok

Abstract:

This paper proposes a digital low-dropout regulator (DLDO)-assisted buck converter featuring one-step computational droop compensation and DLDO feedback-controlled current handover. The 28-nm test chip achieves a 68-mV droop voltage and a 112-ns settling time for a 1A/0.8ns load step while maintaining a high peak efficiency of 95.5%.

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3581844
Publisher: IEEE

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