Voltage

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A 45-V Auto-Zero-Stabilized Chopper Instrumentation Amplifier With 1.8- μ V Offset, 33.5- μ V Ripple, and 42-V Common-Mode Input Range

A 45-V Auto-Zero-Stabilized Chopper Instrumentation Amplifier With 1.8- μ V Offset, 33.5- μ V Ripple, and 42-V Common-Mode Input Range 150 150
Author(s): Jiahao Wang, Shen Ye, Shiqi Zhang, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents a 45V high-precision current-feedback instrumentation amplifier (CFIA) that combines both chopping and auto-zeroing (AZ) to achieve 1.8- $mu $ V input offset (10 samples) and 33.5- $mu $ V input-referred ripple. The AZ is duty cycled to minimize power and silicon area, with a parallel auxiliary path operating during AZ …

Published in: IEEE Solid-State Circuits Letters
Page(s): 173 – 176
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3576393
Publisher: IEEE

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A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique

A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique 150 150
Author(s): Xiangjian Kong, Kai Xu, Huanlin Xie, Mingchao Jian, Hao Lian, Robert Bogdan Staszewski, Chunbing Guo

Abstract:

This article presents a low-jitter sub-sampling chopper phase-locked loop (SS-CPLL) that incorporates a novel chopping charge pump (C-CP) to mitigate 1/f noise in short-channel devices operating at a low supply voltage of 0.75 V. A charge-share cancellation technique is introduced to suppress ripple generated by residual charge from the previous reference …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1384 – 1396
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3532504
Publisher: IEEE

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A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations

A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations 150 150
Author(s): Sayan Kumar, Teerachot Siriburanon, Sumit Dash, Patchara Sawakewang, Shuja Andrabi, Jon Strange, Khurram Muhammad, Chih-Ming Hung, Robert Bogdan Staszewski

Abstract:

We propose a new ping-pong (PP) charge-sharing locking (CSL) phase-locked loop (PLL) architecture that enhances the strength of charge-injection into the oscillator’s LC-tank using complementary charge-sharing capacitors during both positive and negative halves of the reference clock, effectively achieving an implicit $2times $ reference frequency multiplication. The design includes a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1368 – 1383
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3535888
Publisher: IEEE

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A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring

A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring 150 150
Author(s): Junhui Gu, John Ma, Azhar Ahmed Chowdhury, Jianmin Guo, Xin Zhang, Jackson Ding, Hui Wang, Ken Chang

Abstract:

This article presents a high-density, single-ended non return to zero (NRZ) chiplet I/O implemented with 3 nm CMOS technology on a 2.5-D chip-on-wafer-on-substrate (CoWoS) interposer, accommodating trace lengths up to 2 mm. The design features 216 data lanes, each operating at 32 Gb/s. For the tested 2-mm trace, the channel insertion loss …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1289 – 1298
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3545483
Publisher: IEEE

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Device Nonideality-Aware Compute-in-Memory Array Architecting: Direct Voltage Sensing, I–V Symmetric Bitcell, and Padding Array

Device Nonideality-Aware Compute-in-Memory Array Architecting: Direct Voltage Sensing, I–V Symmetric Bitcell, and Padding Array 150 150
Author(s): Jianzi Jin, Shifan Gao, Cimang Lu, Xiang Qiu, Yi Zhao

Abstract:

A voltage sensing compute-in-memory (CIM) architecture has been designed to improve the analog computing accuracy, and a chip on 90-nm flash platform has been successfully fabricated, with the bidirectional operation enabled by the symmetric bitcell structure. By padding the weight sum to a global value for all bit lines (BLs), …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 19 – 24
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3539470
Publisher: IEEE

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Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W

Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W 150 150
Author(s): Yusaku Shiotsu, Satoshi Sugahara

Abstract:

A binarized neural-network (BNN) accelerator macro is developed based on a processing-in-memory (PIM) architecture having the ability of eight-parallel multiply-accumulate (MAC) processing. The parallel-processing PIM macro, referred to as a PPIM macro, is designed to perform the parallel processing with no use of multiport SRAM cells and to achieve the …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 25 – 33
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3538702
Publisher: IEEE

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A Multi-Core Series-Resonance CMOS Oscillator

A Multi-Core Series-Resonance CMOS Oscillator 150 150
Author(s): Shiwei Zhang, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi

Abstract:

Multi-core and series-resonance (SR) techniques have been proposed to achieve ultra-low phase noise (PN) performance. In this article, a scalable ring-coupling scheme is proposed for multi-core expansion. The mechanism provides intrinsic oscillation and PN reduction without compromising the passive network, specifically tailored for the SR oscillator. The dual closed ring …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1644 – 1655
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3529600
Publisher: IEEE

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