Voltage multipliers

A 28-nm System-in-One-Macro Computing-in-Memory Chip Utilizing Leakage-Eliminated 2T1C and Capacitor-Over-Logic 1T1C eDRAM

A 28-nm System-in-One-Macro Computing-in-Memory Chip Utilizing Leakage-Eliminated 2T1C and Capacitor-Over-Logic 1T1C eDRAM 150 150

Abstract:

Computing-in-memory (CIM) is a promising paradigm for energy- and area-efficient implementation of the heavy general matrix multiplication (GEMM) operations, especially in the evolving deep learning algorithms. Though existing CIM macros have demonstrated remarkable energy/area efficiency, the corresponding metrics of the system-level CIM chips degrade due to the peripheral components, …

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A 16-MHz CMOS RC Frequency Reference Achieving Accuracies of ±125 ppm From −40 °C to 85 °C and −560/+580 ppm After Accelerated Aging

A 16-MHz CMOS RC Frequency Reference Achieving Accuracies of ±125 ppm From −40 °C to 85 °C and −560/+580 ppm After Accelerated Aging 150 150

Abstract:

This article presents a low-power, high-accuracy CMOS RC frequency reference featuring a capacitively modulated RC time constant (CMT) generation and a die-to-die error removal (DDER) technique for precise frequency generation with a low-calibration cost. Unlike resistive trimming, the temperature dependence of the on-chip resistor is compensated by a $\Delta \Sigma $ …

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A 6.78-MHz Single-Stage Regulating Rectifier With Dual Outputs Simultaneously Charged in a Half Cycle Achieving 92.2% Efficiency and 131 mW Output Power

A 6.78-MHz Single-Stage Regulating Rectifier With Dual Outputs Simultaneously Charged in a Half Cycle Achieving 92.2% Efficiency and 131 mW Output Power 150 150

Abstract:

Targeting the wireless power transfer (WPT) to implantable medical devices (IMDs), this work presents a 6.78 MHz single-stage dual-output (SSDO) regulating rectifier. It can support the simultaneous charging of both outputs ( $V_{\text {OUT1}}$ and $V_{\text {OUT2}}$ , $V_{\text {OUT1}} \gt V_{\text {OUT2}}$ ) in a half cycle, rather than …

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An 800-MS/s 13-b 2× TI Pipelined-SAR ADC With Rapid Digital Amplification

An 800-MS/s 13-b 2× TI Pipelined-SAR ADC With Rapid Digital Amplification 150 150

Abstract:

This work proposes a rapid digital amplification (RDA) with residue-aware reference, offering an equivalent open-loop (OL) gain enhancement of 25 dB and reducing the interstage gain error (ISGE)-induced SNR degradation by 20 dB, with an extra amplification latency of only 200 ps. It is implemented in an 800-MS/s 13-b two-way time-interleaved (…

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An Ultralow Cross-Regulation Single-Inductor Multiple-Output (SIMO) Buck Converter Using Reordered Power-Distributive Control

An Ultralow Cross-Regulation Single-Inductor Multiple-Output (SIMO) Buck Converter Using Reordered Power-Distributive Control 150 150

Abstract:

A single-inductor multiple-output (SIMO) buck converter employing reordered power-distributive control (RPDC) is presented to achieve ultralow cross regulation. Adedicated power-distribution controller implements RPDC by adaptively adjusting the switching sequence: when the inductor current is insufficient, the switching period is extended, and when excessive, an end phase in the form of …

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A Multiband Ultralow-Power Transceiver With Two-Step Wake-Up Reception

A Multiband Ultralow-Power Transceiver With Two-Step Wake-Up Reception 150 150

Abstract:

This letter presents a multiband fully integrated ultralow-power (ULP) transceiver with a two-step wake-up receiver (WuRX) and switched-capacitor (SC)-based high-efficiency transmitter. Operating from 200 MHz to 1 GHz, the transceiver covers most IoT applications on a single chip. By employing a novel two-step wake-up scheme with a rotating correlator, the proposed …

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PERCEL: A Rewritable NVM CIM Incorporating a CTT-Based Per-Cell DAC

PERCEL: A Rewritable NVM CIM Incorporating a CTT-Based Per-Cell DAC 150 150

Abstract:

Compute-in-memory (CiM) accelerators perform matrix vector multiplications (MVMs) directly inside memory arrays, reducing data movement and improving both energy efficiency and throughput for artificial intelligence (AI) workloads. To reduce the number of conversions, recent designs use multibit compute cells. Nevertheless, practical multibit CiM still faces a tension among accuracy, efficiency, …

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A High-Efficiency Magnetoelectric Power Link With a Load-Adaptive CMOS Rectifier for Miniaturized Implants

A High-Efficiency Magnetoelectric Power Link With a Load-Adaptive CMOS Rectifier for Miniaturized Implants 150 150

Abstract:

Miniaturized biomedical implants are currently constrained by limited wireless power transfer (WPT) efficiency under load variation and spatial misalignment. This work presents a custom magnetoelectric (ME) power link incorporating a load-adaptive CMOS rectifier to address these challenges. By employing a current sensing control loop for dynamic switch sizing and delay …

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