Abstract:
This article presents a wide-lock-in-range and fast-settling-time, 11.6-to-14-GHz subsampling phase-locked loop (PLL) subsampling PLL (SSPLL) using an event-driven frequency-locked loop (ED-FLL) and a harmonic-lock detector (HLD). The ED-FLL becomes active only when a frequency disturbance, $f_{\mathrm {D}}$ , is detected, rapidly corrects the frequency error using a lock-expedition algorithm, …