Very large scale integration

A CMOS Probabilistic Computing Chip with Hardware-Aware Learning

A CMOS Probabilistic Computing Chip with Hardware-Aware Learning 150 150

Abstract:

This work demonstrates a compact probabilistic computing system based on a physics-inspired p-bit architecture with 440 interacting spins configured in a Chimera graph and occupying 0.44 mm² of silicon area. Area efficiency is achieved through a current-mode neuron update circuit and a mixed-signal design approach that integrates pitch-matched standard-cell analog blocks with …

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A 16-MHz CMOS RC Frequency Reference Achieving Accuracies of ±125 ppm From −40 °C to 85 °C and −560/+580 ppm After Accelerated Aging

A 16-MHz CMOS RC Frequency Reference Achieving Accuracies of ±125 ppm From −40 °C to 85 °C and −560/+580 ppm After Accelerated Aging 150 150

Abstract:

This article presents a low-power, high-accuracy CMOS RC frequency reference featuring a capacitively modulated RC time constant (CMT) generation and a die-to-die error removal (DDER) technique for precise frequency generation with a low-calibration cost. Unlike resistive trimming, the temperature dependence of the on-chip resistor is compensated by a $\Delta \Sigma $ …

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A 40k-Pixel Multimodal Biophysiology Monitoring Platform With 10k Concurrent Electrophysiology Channels and a Mixer-Embedded ΣΔ Impedance Sensor

A 40k-Pixel Multimodal Biophysiology Monitoring Platform With 10k Concurrent Electrophysiology Channels and a Mixer-Embedded ΣΔ Impedance Sensor 150 150

Abstract:

Understanding complex physiological processes requires the ability to monitor multiple biological modalities concurrently, as electrical, ionic, and biochemical processes are tightly coupled and cannot be holistically described by single-mode sensors. This article presents a 40 nm CMOS multimodal cellular physiology monitoring platform that integrates 40 960 reconfigurable pixels at $10.8~\mu $ m pixel pitch. …

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An 800-MS/s 13-b 2× TI Pipelined-SAR ADC With Rapid Digital Amplification

An 800-MS/s 13-b 2× TI Pipelined-SAR ADC With Rapid Digital Amplification 150 150

Abstract:

This work proposes a rapid digital amplification (RDA) with residue-aware reference, offering an equivalent open-loop (OL) gain enhancement of 25 dB and reducing the interstage gain error (ISGE)-induced SNR degradation by 20 dB, with an extra amplification latency of only 200 ps. It is implemented in an 800-MS/s 13-b two-way time-interleaved (…

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Self-Enabled Write Assist Cells for High-Density SRAM in Resistance-Dominated Technology Node

Self-Enabled Write Assist Cells for High-Density SRAM in Resistance-Dominated Technology Node 150 150

Abstract:

As technology scaling increases interconnect resistance, writeability degradation in static random access memory (SRAM) becomes critical. This article presents a self-enabled write assist cell (SEWAC) that mitigates writeability degradation caused by increased bitline resistance (R ${}_{\mathrm {BL}}$ ) without requiring timing control. The SEWAC has a cell-compatible layout with the standard 6…

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A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction 150 150

Abstract:

This article presents a 2-read/write (2RW) pseudo dual-port (PDP) static random access memory (SRAM) macro implemented in advanced 3nm Fin-FET technology, achieving a competitive bit density of 19.87Mbit/mm2 for advanced nodes. To address challenges in process scaling, reliability under process voltage temperature variations, and dynamic power consumption, two …

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A Continuous-Time Zoom Sensor Readout Frontend With Fast Tracking and Floating-Gm-CCO Integrator

A Continuous-Time Zoom Sensor Readout Frontend With Fast Tracking and Floating-Gm-CCO Integrator 150 150

Abstract:

Emerging edge applications processing weak signals in noisy environments demand sensor readout frontends with low noise, low power, high dynamic range (DR), and high input impedance. This article presents a zoom sensor readout frontend design that can track signals with rapid changes over a wide DR with high energy efficiency. …

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A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference

A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference 150 150

Abstract:

Static random-access memory (SRAM)-based computing-in-memory (CIM) macros have been widely studied to improve the energy efficiency of edge artificial intelligence (AI) inference tasks. However, less attention has been given to AI training, which requires CIM macros to not only perform matrix multiply-accumulate (MAC) operations but also support matrix transposition. …

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A Wide-Dynamic-Range Photovoltaic Energy Harvester With Adaptive Power-Scalable MPPT Control and Direct Power-to-Digital Converter

A Wide-Dynamic-Range Photovoltaic Energy Harvester With Adaptive Power-Scalable MPPT Control and Direct Power-to-Digital Converter 150 150

Abstract:

This article presents a photovoltaic energy harvester (PVEH) that achieves high maximum power point tracking (MPPT) efficiency and power conversion efficiency across a $100~000{\times }$ input power dynamic range (DR) (from $10~{\mu }$ W to 1W). Wide-dynamic-range operation is challenging due to the inherent tradeoff between MPPT accuracy and controller power consumption. …

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