Very large scale integration

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A CMOS Probabilistic Computing Chip With Hardware-Aware Learning

A CMOS Probabilistic Computing Chip With Hardware-Aware Learning 150 150
Author(s): Jinesh Jhonsa, William Whitehead, Yihao Wu, David Mccarthy, Shuvro Chowdhury, Kerem Y. Camsari, Luke Theogarajan

Abstract:

This work demonstrates a compact probabilistic computing system based on a physics-inspired probabilistic bit (p-bit) architecture with 440 interacting spins configured in a chimera graph and occupying 0.44 mm2 of silicon area. Area efficiency is achieved through a current-mode neuron update circuit and a mixed-signal design approach that integrates pitch-matched standard-cell analog …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 86 – 94
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3689506
Publisher: IEEE

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OISMA: On-the-Fly In-Memory Stochastic Multiplication Architecture for Approximate Matrix Multiplication

OISMA: On-the-Fly In-Memory Stochastic Multiplication Architecture for Approximate Matrix Multiplication 150 150
Author(s): Shady Agwa, Yihan Pan, Georgios Papandroulidakis, Themis Prodromakis

Abstract:

Artificial intelligence (AI) models are currently driven by a significant upscaling of their complexity, with massive matrix-multiplication workloads representing the major computational bottleneck. In-memory computing (IMC) architectures are proposed to avoid the von Neumann bottleneck. However, both digital/binary-based and analog IMC architectures suffer from various limitations, which significantly degrade …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 56 – 64
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3680281
Publisher: IEEE

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A Complementary Positive Feedback-Assisted Current Mirror-Based Level Shifter for Energy-Efficient Level Conversion for Wide Voltage Ranges

A Complementary Positive Feedback-Assisted Current Mirror-Based Level Shifter for Energy-Efficient Level Conversion for Wide Voltage Ranges 150 150
Author(s): Shin Han, Gicheol Shin, Jongmin Lee, Yoonmyung Lee

Abstract:

A complementary positive feedback-assisted current mirror-based level shifter (CPFLS) is proposed to reliably convert subthreshold signals to higher voltages. By adopting a positive feedback structure, the CPFLS mitigates the delay degradation and short-circuit current issues inherent in a prior art, WCMLS, due to its negative feedback design. Additionally, the CPFLS …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3687258
Publisher: IEEE

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A 16-MHz CMOS RC Frequency Reference Achieving Accuracies of ±125 ppm From −40 °C to 85 °C and −560/+580 ppm After Accelerated Aging

A 16-MHz CMOS RC Frequency Reference Achieving Accuracies of ±125 ppm From −40 °C to 85 °C and −560/+580 ppm After Accelerated Aging 150 150
Author(s): Runtao Huo, Weihao Jie, Yiwen Zhang, Honglan Jiang, Hui Wang

Abstract:

This article presents a low-power, high-accuracy CMOS RC frequency reference featuring a capacitively modulated RC time constant (CMT) generation and a die-to-die error removal (DDER) technique for precise frequency generation with a low-calibration cost. Unlike resistive trimming, the temperature dependence of the on-chip resistor is compensated by a $\Delta \Sigma $ …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3684094
Publisher: IEEE

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A 40k-Pixel Multimodal Biophysiology Monitoring Platform With 10k Concurrent Electrophysiology Channels and a Mixer-Embedded ΣΔ Impedance Sensor

A 40k-Pixel Multimodal Biophysiology Monitoring Platform With 10k Concurrent Electrophysiology Channels and a Mixer-Embedded ΣΔ Impedance Sensor 150 150
Author(s): Hangxing Liu, Fuze Jiang, Jingjing Zang, Marco Saif, Thomas Burger, Stephan C. F. Neuhauss, Hua Wang

Abstract:

Understanding complex physiological processes requires the ability to monitor multiple biological modalities concurrently, as electrical, ionic, and biochemical processes are tightly coupled and cannot be holistically described by single-mode sensors. This article presents a 40 nm CMOS multimodal cellular physiology monitoring platform that integrates 40 960 reconfigurable pixels at $10.8~\mu $ m pixel pitch. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3684715
Publisher: IEEE

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An 800-MS/s 13-b 2× TI Pipelined-SAR ADC With Rapid Digital Amplification

An 800-MS/s 13-b 2× TI Pipelined-SAR ADC With Rapid Digital Amplification 150 150
Author(s): Peizhe Li, Danfeng Zhai, Qi Liu, Chixiao Chen

Abstract:

This work proposes a rapid digital amplification (RDA) with residue-aware reference, offering an equivalent open-loop (OL) gain enhancement of 25 dB and reducing the interstage gain error (ISGE)-induced SNR degradation by 20 dB, with an extra amplification latency of only 200 ps. It is implemented in an 800-MS/s 13-b two-way time-interleaved (…

Published in: IEEE Solid-State Circuits Letters
Page(s): 137 – 140
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3684735
Publisher: IEEE

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Self-Enabled Write Assist Cells for High-Density SRAM in Resistance-Dominated Technology Node

Self-Enabled Write Assist Cells for High-Density SRAM in Resistance-Dominated Technology Node 150 150
Author(s): Minjune Yeo, Seungjae Yei, Keonhee Cho, Giseok Kim, Mingu Kang, Seong-Ook Jung

Abstract:

As technology scaling increases interconnect resistance, writeability degradation in static random access memory (SRAM) becomes critical. This article presents a self-enabled write assist cell (SEWAC) that mitigates writeability degradation caused by increased bitline resistance (R ${}_{\mathrm {BL}}$ ) without requiring timing control. The SEWAC has a cell-compatible layout with the standard 6…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3681916
Publisher: IEEE

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A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction 150 150
Author(s): Tomotaka Tanaka, Koji Nii, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Abstract:

This article presents a 2-read/write (2RW) pseudo dual-port (PDP) static random access memory (SRAM) macro implemented in advanced 3nm Fin-FET technology, achieving a competitive bit density of 19.87Mbit/mm2 for advanced nodes. To address challenges in process scaling, reliability under process voltage temperature variations, and dynamic power consumption, two …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3682256
Publisher: IEEE

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A Continuous-Time Zoom Sensor Readout Frontend With Fast Tracking and Floating-Gm-CCO Integrator

A Continuous-Time Zoom Sensor Readout Frontend With Fast Tracking and Floating-Gm-CCO Integrator 150 150
Author(s): Haoyang Luo, Zongnan Wang, Jiarui Wang, Bingrui Li, Zilong Shen, Yang Liu, Xiaojie Duan, Yuan Wang, Xiyuan Tang

Abstract:

Emerging edge applications processing weak signals in noisy environments demand sensor readout frontends with low noise, low power, high dynamic range (DR), and high input impedance. This article presents a zoom sensor readout frontend design that can track signals with rapid changes over a wide DR with high energy efficiency. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3677053
Publisher: IEEE

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