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A 65 nm Privacy-Preserving Neuromorphic Encoder With 7.13 nJ Efficiency, 2.38 Mb/mm2 2T–2T Item Memory Density and Federated Learning Support

A 65 nm Privacy-Preserving Neuromorphic Encoder With 7.13 nJ Efficiency, 2.38 Mb/mm2 2T–2T Item Memory Density and Federated Learning Support 150 150
Author(s): Boyang Cheng, Jianbo Liu, Steven Davis, Zephan M. Enciso, Likai Pei, Xueji Zhao, Muya Chang, Ningyuan Cao

Abstract:

The increasing demand for privacy-preserving personal data analytics in smart assistants and context-aware systems necessitates hardware that is both energy-efficient and secure. This work presents a 65 nm privacy-preserving neuromorphic encoder that addresses these challenges through physically uncloneable and hardware-efficient encoding. At the core of the architecture is a 2T–2T …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721817
Publisher: IEEE

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Antiferromagnetic Programmable Neuron: Structure, Training, and Pattern Recognition Applications

Antiferromagnetic Programmable Neuron: Structure, Training, and Pattern Recognition Applications 150 150
Author(s): I. Sotnyk, O. Prokopenko

Abstract:

Artificial neurons based on antiferromagnetic (AFM) spin Hall oscillators (SHOs) are promising elements for creating ultrafast, energy-efficient neuromorphic computing systems. These structures can generate picosecond spikes in response to dc and ac electric currents, thereby mimicking the reaction of biological neurons to an external stimulus. However, conventional AFM neurons have …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 9 – 17
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3633490
Publisher: IEEE

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Birch: A Real-Time Multi-Domain Multi-Task Extended Reality Perception Accelerator

Birch: A Real-Time Multi-Domain Multi-Task Extended Reality Perception Accelerator 150 150
Author(s): Kathleen Feng, Kai Bartolone, Kartik Prabhu, Brianna McColm, Xingyu Ni, Siddhant Gupta, Priyanka Raina

Abstract:

Birch is a system-on-chip (SoC) that efficiently and accurately accelerates the multi-task multi-domain extended reality (XR) perception pipeline, with workloads such as visual inertial odometry (VIO), eye gaze tracking, and scene understanding. Birch features vision modules with cascaded line buffers, in-step feature sorting, and double-buffered optical flow to extract and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 121 – 124
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3673168
Publisher: IEEE

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EMO-CIM: An Input/Stationary-Data Similarity-Aware Computing-In-Memory Design for Variable Vector-Wise Computation in Edge Multioperator AI Acceleration

EMO-CIM: An Input/Stationary-Data Similarity-Aware Computing-In-Memory Design for Variable Vector-Wise Computation in Edge Multioperator AI Acceleration 150 150
Author(s): Bo Wang, Yuchen Tang, Feiran Liu, Xiaoxue Zhong, Yuchen Ma, Xin Si, Jun Yang

Abstract:

We propose an edge multioperator computing-in-memory (EMO-CIM) design that supports variable vector-wise multiply-and-accumulate (MAC) in CNN, Depthwise (DW)-Convolution, and Attention operators. It features: 1) a single EMO-CIM bank (ECB) excels in variable vector-wise MAC (V-MAC) for multioperators; 2) merging local input-shared compute units (LISCUs) with a decode-unit and adder-tree (DUAT) facilitates …

Published in: IEEE Solid-State Circuits Letters
Page(s): 97 – 100
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3668853
Publisher: IEEE

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An Electrophysiology-Optogenetics Closed-Loop Bi-Directional Neural Interface for Sleep Regulation With 0.2-μJ/class Multiplexer-Based Neural Network

An Electrophysiology-Optogenetics Closed-Loop Bi-Directional Neural Interface for Sleep Regulation With 0.2-μJ/class Multiplexer-Based Neural Network 150 150
Author(s): Chao Zhang, Fenyan Zhang, Dawid Sheng, Zhixiong Ma, Yongxiang Guo, Chao Sun, Yuwei Zhang, Wenxin Zhao, Xing Sheng, Tongfei A. Wang, Milin Zhang

Abstract:

This work proposed a multiplexer-based neural network (MUXnet), a multiplexer-based, multiplier-free neural network (NN) structure applicable to the implementation of all inner product-based NN layers. An on-chip MUXnet-based neural signal processing unit (NSPU) was designed, achieving a state-of-the-art accuracy of 82.4% on a public human sleep staging dataset, with the lowest …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3639446
Publisher: IEEE

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Side-Channel Attack-Resistant HMAC-SHA256 Accelerator With Boolean and Arithmetic Masking in Intel 4 CMOS

Side-Channel Attack-Resistant HMAC-SHA256 Accelerator With Boolean and Arithmetic Masking in Intel 4 CMOS 150 150
Author(s): Sachin Taneja, Vikram B. Suresh, Raghavan Kumar, Vivek De, Sanu K. Mathew

Abstract:

This work describes a side-channel attack (SCA)-resistant hash-based message authentication code (HMAC) accelerator with secure hash algorithm 2 (SHA-2) using Boolean and arithmetic masking along with the first-reported ASIC implementation in Intel 4 CMOS with 10 M measured traces. Previously reported masked datapath suffers from high area/performance overheads (>100%) designs due to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1026 – 1036
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3647096
Publisher: IEEE

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Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data

Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data 150 150
Author(s): Douwe den Blanken, Charlotte Frenkel

Abstract:

On-device learning at the edge enables low-latency, private personalization with improved long-term robustness and reduced maintenance costs. Yet, achieving scalable, low-power (LP) end-to-end on-chip learning, especially from real-world sequential data with a limited number of examples, is an open challenge. Indeed, accelerators supporting error backpropagation optimize for learning performance at …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3645640
Publisher: IEEE

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A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC

A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC 150 150
Author(s): Vaidehi Garg, Jianwei Jia, Omkar Phadke, Shimeng Yu

Abstract:

Compute-in-memory (CIM) using emerging nonvolatile memory devices is a promising candidate for energy-efficient deep neural network (DNN) inference at the edge. Ferroelectric field-effect transistors (FeFETs) have recently gained attention as nonvolatile, CMOS-compatible devices with a higher on/off ratio and lower read and write energy compared to resistive random-access memory (…

Published in: IEEE Solid-State Circuits Letters
Page(s): 13 – 16
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3640522
Publisher: IEEE

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A Multicore Programmable Variable-Precision Near-Memory Accelerator for CNN and Transformer Models

A Multicore Programmable Variable-Precision Near-Memory Accelerator for CNN and Transformer Models 150 150
Author(s): Yiming Yang, Yiyang Yuan, Xinghua Wang, Xiaoran Li, Hao Wu, Qihao Liu, Weiye Tang, Xiangqu Fu, Feng Zhang

Abstract:

Convolutional neural network (CNN) and transformer are the most popular neural network models in computer vision (CV) and natural language processing (NLP). It is quite common to use both these two models in multimodal scenarios, such as text-to-image generation. However, these two models have very different memory mappings, dataflows and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3624011
Publisher: IEEE

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