variable gain amplifier (VGA)

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A Ka-Band Time-Modulated Phase-Invariant Variable-Gain Amplifier With 30-dB Gain Tuning Based on Duty-Cycle Control

A Ka-Band Time-Modulated Phase-Invariant Variable-Gain Amplifier With 30-dB Gain Tuning Based on Duty-Cycle Control 150 150
Author(s): Dongfan Xu, Minzhe Tang, Haiyun Gu, Yuxuan Liu, Yilun Chen, Ziyuan Ren, Minghao Fan, Daxu Zhang, Yi Zhang, Duo Li, Zheng Li, Zezheng Liu, Chun Wang, Yudai Yamazaki, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a time-modulated variable-gain amplifier (VGA) employing a clock-sampling topology governed by a duty-cycle control (DCC) loop. By modulating the effective operation time of the amplifier rather than altering its RF bias conditions, for precise tuning of the clock duty cycle, enabling phase consistency at millimeter-wave frequencies. The …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3695362
Publisher: IEEE

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A 48-Gb/s Inductorless PAM-4 Optical Receiver With 1.28-pJ/bit Efficiency in 28-nm CMOS

A 48-Gb/s Inductorless PAM-4 Optical Receiver With 1.28-pJ/bit Efficiency in 28-nm CMOS 150 150
Author(s): Chongyun Zhang, Li Wang, Fuzhan Chen, Quan Pan, Xianbo Li, C. Patrick Yue

Abstract:

This work presents a 48-Gb/s four-level pulse amplitude modulation (PAM-4) optical receiver (ORX) with a linear analog front-end (AFE) and an integrated sampler. The AFE employs a transadmittance-stage transimpedance-stage (TAS-TIS) topology, replacing conventional CML-based variable gain amplifiers (VGAs) and post-amplifiers, avoiding continuous-time linear equalizers and passive inductors while preserving …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3607107
Publisher: IEEE

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A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS

A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS 150 150
Author(s): Chongyun Zhang, Li Wang, Fuzhan Chen, C. Patrick Yue

Abstract:

This letter presents a 0.32 pJ/bit 100-Gb/s PAM-4 CMOS transimpedance amplifier (TIA). Several techniques are proposed to alleviate TIA design tradeoffs while pushing energy efficiency to a limit. A multipeaking input network is designed to relieve the bandwidth (BW) degradation from parasitics of input interface and ESD diodes. An …

Published in: IEEE Solid-State Circuits Letters
Page(s): 273 – 276
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3603569
Publisher: IEEE

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