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kNOT: A 2-D Distributed Network-on-Textile Architecture With Direct Die-to-Yarn Integration of 0.6 × 2.15 mm2 SoC and bySPI Chiplets for Wearable Computing

kNOT: A 2-D Distributed Network-on-Textile Architecture With Direct Die-to-Yarn Integration of 0.6 × 2.15 mm2 SoC and bySPI Chiplets for Wearable Computing 150 150
Author(s): Anjali Agrawal, Zhenghong Chen, Braden E. Desman, Jinhua Wang, Akiyoshi Tanaka, Fahim Foysal, Charles D. Hess, Will Farrell, Jim Owens, Daniel S. Truesdell, Benton H. Calhoun

Abstract:

This article presents kNOT, a scalable, distributed, and 2-D Network-On-Textile (kNOT) comprising miniaturized systems on chip (SoCs) and bypass SPI (bySPI) networking chiplets that together enable diverse networking and computational tasks. To preserve garment comfort and flexibility, kNOT eliminates bulky boards and interposers through direct-die attachment to embroidered yarns. The …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 103 – 115
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3624099
Publisher: IEEE

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A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core

A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core 150 150
Author(s): Berkay Özbek, Timothy G. Constandinou

Abstract:

This letter presents an adaptable ring oscillator (RO)-true random number generator (TRNG) that removes the fixed power–throughput tradeoff by selecting delay-cell physics at run time. A hybrid core uses a current-starved inverter in low-power (LP) mode to amplify slew-limited jitter for high bit-efficiency at low frequency, and a …

Published in: IEEE Solid-State Circuits Letters
Page(s): 325 – 328
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3621413
Publisher: IEEE

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A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS

A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS 150 150
Author(s): Chongyun Zhang, Li Wang, Fuzhan Chen, C. Patrick Yue

Abstract:

This letter presents a 0.32 pJ/bit 100-Gb/s PAM-4 CMOS transimpedance amplifier (TIA). Several techniques are proposed to alleviate TIA design tradeoffs while pushing energy efficiency to a limit. A multipeaking input network is designed to relieve the bandwidth (BW) degradation from parasitics of input interface and ESD diodes. An …

Published in: IEEE Solid-State Circuits Letters
Page(s): 273 – 276
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3603569
Publisher: IEEE

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Reconfigurable Ferroelectric Bandpass Filter With Low-Frequency Noise Analysis for Intracardiac Electrogram Monitoring

Reconfigurable Ferroelectric Bandpass Filter With Low-Frequency Noise Analysis for Intracardiac Electrogram Monitoring 150 150
Author(s): Jianwei Jia, Zhenge Jia, Omkar Phadke, Yiyu Shi, Shimeng Yu

Abstract:

Implantable cardioverter defibrillators (ICDs) provide real-time monitoring and immediate defibrillation for life-threatening arrhythmias. However, the intracardiac electrogram (IEGM) acquisition of ICDs faces stringent constraints, including power consumption, low-frequency noise, and patient-specific physiological variability. This article introduces an ultralow-power, high-resolution, reconfigurable three-stage bandpass filter designed specifically for IEGM, utilizing ferroelectric field-effect …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 67 – 73
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3584711
Publisher: IEEE

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A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique

A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique 150 150
Author(s): Sungjin Kim, Jeonghyun Lee, Yoonse Cho, Jintae Kim, Jaehyouk Choi, Heein Yoon

Abstract:

This letter presents a 7-bit pipelined subranging ADC that integrates a 3-bit flash ADC with a ring VCO-based quantizer. A resistor-ladder-based residue shifter (RLRS) replaces traditional residue amplifiers, efficiently shifting the residue voltage into the most linear region of the $K_{textrm {VCO}}$ , thereby eliminating the need for post-linearity calibration. …

Published in: IEEE Solid-State Circuits Letters
Page(s): 177 – 180
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3578546
Publisher: IEEE

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A Simultaneous Dual-Carrier Transformer-Coupled Passive Mixer-First Receiver Front-End Supporting Blocker Suppression

A Simultaneous Dual-Carrier Transformer-Coupled Passive Mixer-First Receiver Front-End Supporting Blocker Suppression 150 150
Author(s): Jamie C. Ye, Alain H. Antón, Sanaz Sadeghi, Russ H. Huang, Alyosha C. Molnar

Abstract:

A high dynamic range N-path passive mixer-first receiver architecture capable of simultaneously down-converting two arbitrary bands through a single RF port is presented. The architecture consists of two passive mixers arranged in a series configuration with a transformer front-end to minimize cross-loading between mixers while still providing impedance transparency and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1541 – 1553
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3546082
Publisher: IEEE

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A Multi-Core Series-Resonance CMOS Oscillator

A Multi-Core Series-Resonance CMOS Oscillator 150 150
Author(s): Shiwei Zhang, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi

Abstract:

Multi-core and series-resonance (SR) techniques have been proposed to achieve ultra-low phase noise (PN) performance. In this article, a scalable ring-coupling scheme is proposed for multi-core expansion. The mechanism provides intrinsic oscillation and PN reduction without compromising the passive network, specifically tailored for the SR oscillator. The dual closed ring …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1644 – 1655
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3529600
Publisher: IEEE

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