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A 6-bit Serializer With Integrated Manchester Encoder Using Flexible a-IGZO TFT Technology

A 6-bit Serializer With Integrated Manchester Encoder Using Flexible a-IGZO TFT Technology 150 150
Author(s): Suyash Shrivastava, Pydi Ganga Bahubalindruni

Abstract:

This article presents an experimental characterization of a novel 6-bit parallel-to-serial data converter integrated with a Manchester encoder. The system comprises an on-chip digital logic block that generates six mutually nonoverlapping control signals ( $\phi _{0-5}$ ) and three 120° phase-shifted clock signals to drive the switching transistors in the serializer and the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 194 – 197
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3707465
Publisher: IEEE

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A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications

A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications 150 150
Author(s): Maysara Hamada, Mostafa Toubar, Zixu Wang, Nishant Bakshi, Hsiang-Chun Cheng, Mayank Palaria, Joshua Yang, Mike Shuo-Wei Chen

Abstract:

As crossbar-based analog computing grows in popularity for high-speed, energy-efficient processing, the need to drive discrete-time signals to heavy loads arises. This paper presents a novel bi-slewing CMOS driver utilizing high slew-rate error amplifiers and a push-pull stage. The proposed driver achieves a measured settling time of 8.5 ns and a …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3717852
Publisher: IEEE

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Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM

Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM 150 150
Author(s): Kiseok Lee, Seongkwang Lim, Suman Datta, Shimeng Yu

Abstract:

Processing-in-memory (PIM) by implementing Boolean logic functions in dynamic random access memory (DRAM) has been proposed to alleviate the memory wall problem in data-intensive computing. However, quantitatively evaluating DRAM-based logic operations across different DRAM architectures remains challenging due to the lack of publicly available DRAM cell and peripheral transistor models …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 144 – 152
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704508
Publisher: IEEE

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Probabilistic Computing With Neuromorphic Elements

Probabilistic Computing With Neuromorphic Elements 150 150
Author(s): Zonglong Li, Laurie E. Calvet

Abstract:

This article presents a compact and low-power approach to probabilistic inference based on time-domain analog computation. The proposed system implements a Bayesian classifier using neuromorphic circuit elements simulated in a 130-nm CMOS technology. Probabilities are encoded in the duty cycle of deterministic spiking signals generated by neuron circuits, while likelihood …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 167 – 175
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3712198
Publisher: IEEE

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A Tunable RF Self-Interference Canceller With Highly Accelerated, Machine-Learning-Based Adaptation for Full-Duplex Radio Applications

A Tunable RF Self-Interference Canceller With Highly Accelerated, Machine-Learning-Based Adaptation for Full-Duplex Radio Applications 150 150
Author(s): Xichen Li, Ahmed Refaat Aboulsaad, Elpida Karapepera, Yi-Hsiang Huang, Po-Hao Cheng, Charles Chien, Jacques Christophe Rudell

Abstract:

Future full-duplex (FD) radio systems require highly tunable self-interference (SI) cancellers with rapid adaptation to mitigate dynamic SI profiles in wireless environments. This article presents a 2.4-GHz RF SI canceller chip with extensive tuning capabilities that operates with a machine-learning (ML)-augmented adaptation loop for FD transceivers. The proposed design …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715631
Publisher: IEEE

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P-Dits for the Frequency Assignment Problem With Transmitter Deactivation in Dense Environments

P-Dits for the Frequency Assignment Problem With Transmitter Deactivation in Dense Environments 150 150
Author(s): Christian Duffee, Jordan Athas, Igor Kadota, Randall Berry, Pedram Khalili Amiri

Abstract:

The frequency assignment problem is a nondeterministic polynomial-time hard (NP-hard) optimization problem concerning the assignment of frequency channels to wireless transmitters. Typically, the aim is to minimize interference between transmitters while maintaining a high level of service. In this work, the use of probabilistic d-dimensional bits, or p-dits, for this …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 78 – 85
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3690563
Publisher: IEEE

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TD-dAJC: A 100 MS/s 2 pJ/Pixel Time-Domain Weight and Integrating-MAC-Based Direct Analog to MJPEG Compression for Video Sensor Nodes

TD-dAJC: A 100 MS/s 2 pJ/Pixel Time-Domain Weight and Integrating-MAC-Based Direct Analog to MJPEG Compression for Video Sensor Nodes 150 150
Author(s): Harshit Naman, Gourab Barik, Yudhajit Ray, Shreyas Sen

Abstract:

Always-on, high-quality video sensors are increasingly required in wearables, surveillance, and Internet-of-Things (IoT) devices, where stringent energy constraints make efficient in-sensor compression necessary. These systems must support high-definition (HD) and 4 K video, yet conventional digital video compression pipelines consume significant power because high-speed analog-to-digital converters (ADCs) must digitize every pixel, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3712196
Publisher: IEEE

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A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC with Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration

A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC with Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration 150 150
Author(s): Jiazhen Ni, Dayi Zhou, Minqing Cai, Chen Chen, Xiang Gao, Seung-Chul Lee

Abstract:

Successive approximation register (SAR) analog-to-digital converters (ADCs) often employ dual-mode dynamic comparators to achieve both high speed and low noise. However, under low-supply operation, offset drift from mode transitions and degraded front-end linearity due to limited signal headroom become critical challenges. To address these issues, an adaptive current-injection scheme suppresses …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3713349
Publisher: IEEE

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A 96 × 64 SPAD LiDAR Sensor With 6× Imaging FoM Promotion by AI-Assisted Fusion of 2-D and Edge-Guided Sparse 3-D Detection

A 96 × 64 SPAD LiDAR Sensor With 6× Imaging FoM Promotion by AI-Assisted Fusion of 2-D and Edge-Guided Sparse 3-D Detection 150 150
Author(s): Bu Chen, Qi Zheng, Zikun Cai, Hankun Lv, Jingyi Wang, Jun Han, Zhangcheng Huang, Jianlu Wang, Qi Liu, Ming Liu

Abstract:

Flash-mode direct time-of-flight (dToF) light detection and ranging (LiDAR) is widely adopted in autonomous systems and robotics due to its capability for accurate depth measurement and robustness under challenging lighting conditions. However, scaling single-photon avalanche diode (SPAD)-based dToF pixel arrays toward higher resolution 3-D imaging introduces significant challenges in …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3714508
Publisher: IEEE

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