Timing

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A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC

A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC 150 150
Author(s): Daxu Zhang, Yuncheng Zhang, Zezheng Liu, Yuang Xiong, Wenqian Wang, Duo Li, Minzhe Tang, Dongfan Xu, Dingxin Xu, Kazuaki Kunihiro, Hiroyuki Sakai, Kenichi Okada

Abstract:

This letter presents a fractional-N digital phase-locked loop (DPLL) employing a dynamic-threshold digital-to-time converter (DT-DTC). By dynamically adjusting the comparator threshold voltage, the proposed DT-DTC mitigates delay nonlinearity without digital predistortion (DPD). A quadrature-VCO (QVCO) generates quadrature phases for a multiphase clock generator (MPCG). The QVCO-based MPCG with skew calibration …

Published in: IEEE Solid-State Circuits Letters
Page(s): 250 – 253
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3725284
Publisher: IEEE

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A Delay-Compensated RC Oscillator With Constant Ramp Peak-Voltage Achieving 23 ppm/°C Temperature Coefficient from -40 to 100 °C

A Delay-Compensated RC Oscillator With Constant Ramp Peak-Voltage Achieving 23 ppm/°C Temperature Coefficient from -40 to 100 °C 150 150
Author(s): Wenbo Zhang, Fantao Wang, Junyi Liu, Yanzhao Ma

Abstract:

This letter presents a delay-compensated RC relaxation oscillator for enhanced frequency stability. The proposed architecture employs a peak-sampling circuit to detect the charging-capacitor peak voltage. A feedback loop composed of an error amplifier and compensation resistors adaptively raises the capacitor DC baseline to compensate for comparator-delay-induced frequency error, while phase-alternating …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3738818
Publisher: IEEE

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Temperature-Dependent Soft-Error Analysis from 300K to 77K in Nanosheet and CFET

Temperature-Dependent Soft-Error Analysis from 300K to 77K in Nanosheet and CFET 150 150
Author(s): Sufia Shahin, Hafeez Raza, Avinash Lahgere, Yogesh Singh Chauhan, Hussam Amrouch

Abstract:

We investigate the impact of cryogenic temperatures on the Single Event Upset (SEU) reliability of the Gate-All-Around (GAA) Nanosheet FET (NSFET) and Complementary FET (CFET) devices. At the device level, we assess heavy-ion radiation (HIR)-induced transients and carrier profiles and compare CFET and NSFET at temperatures from 400K to 77 …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740550
Publisher: IEEE

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Nanoelectromechanically Gated Gain Cell eDRAM

Nanoelectromechanically Gated Gain Cell eDRAM 150 150
Author(s): Collin P. Finnan, Choong-Ho Rhee, Tahir Ghani, Tsu-Jae King-Liu

Abstract:

The memory wall and the slowdown of static random access memory (SRAM) scaling have renewed interest in gain-cell embedded dynamic random access memory (DRAM). While gain cells offer high density and energy efficiency, they suffer from limited retention, parasitic coupling, and the need for boosted write voltages. This work introduces …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 223 – 230
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3717204
Publisher: IEEE

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A Threshold-Voltage Self-Compensated Dual-Gate IGZO TFT Cell for Robust In-Sensor Computing

A Threshold-Voltage Self-Compensated Dual-Gate IGZO TFT Cell for Robust In-Sensor Computing 150 150
Author(s): Zhi Li, Zikang Mei, Wei Tang

Abstract:

In-sensor computing (ISC) based on amorphous metal-oxide thin-film transistors (TFTs) promises compact, high-density vision chips, yet large-scale integration is vulnerable to process-induced threshold-voltage ( $V_{th}$ ) variations that critically degrade computational robustness and accuracy. This work proposes a novel 3T1C (3-Transistor, 1-Capacitor) ISC cell circuit based on photodiode (PD)-gated …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 214 – 222
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3736074
Publisher: IEEE

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A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion

A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion 150 150
Author(s): Peng Wang, Yaning Wang, Fule Li, Zhihua Wang

Abstract:

This article presents a 12-bit, 1-GS/s SAR-assisted pipelined ADC implemented in 28-nm CMOS featuring accurate residue amplification (RA) with low gain variation. A dual-path residue amplifier embeds an open-loop gain-error-cancellation path within the closed-loop amplification path, providing accurate gain and robust gain stability without additional timing or power overhead. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5706 – 5719
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713446
Publisher: IEEE

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A Current-Mode Nondestructive Circuit Readout Scheme for High-Density 3-D Ferroelectric Memory

A Current-Mode Nondestructive Circuit Readout Scheme for High-Density 3-D Ferroelectric Memory 150 150
Author(s): Chaohan Wang, Wagdy Hussein, Yang Xiang, Shankha Mukherjee, Ismail Cevik, Fernando García-Redondo, Annachiara Spagnolo, Hyungrock Oh, Marie Garcia Bardon, Nick van Helleputte, Julien Ryckaert, Geert Hellings, Dwaipayan Biswas, Jan van Houdt

Abstract:

The AI era is demanding ever-increasing memory capacity and bandwidth, where 3-D-stacked ferroelectric memory (FeRAM) utilizing nondestructive readout (NDRO) ferroelectric capacitors (FeCAPs) stand as a promising candidate. This work addresses NDRO sensing signal challenges in deeply scaled 3-D FeRAMs using a current-mode sensing scheme, co-designed with the device architecture to …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 199 – 204
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3727137
Publisher: IEEE

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HEMAIA: A 16 nm Heterogeneous Multi-Accelerator SoC With Accelerator-Centric Execution

HEMAIA: A 16 nm Heterogeneous Multi-Accelerator SoC With Accelerator-Centric Execution 150 150
Author(s): Ryan Antonio, Xiaoling Yi, Jun Yin, Ce Ma, Yunhao Deng, Fanchen Kong, Abdelrahman Ayman Fathallah, Joren Dumoulin, Josse van Delm, Tiago Knorst, Adrian Kneip, Guilherme Paim, Wim Dehaene, Marian Verhelst

Abstract:

Emerging heterogeneous AI workloads span classic computer vision, modern transformers, and complex neuro-symbolic (NeSy) pipelines. These workloads demand multi-accelerator SoCs that integrate uniquely designed engines and orchestrate them efficiently. Two systemic bottlenecks arise from existing heterogeneous SoCs: 1) mismatched accelerator data access patterns, spanning bandwidth, dataflow, and data layout, reduce effective …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 19
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3739314
Publisher: IEEE

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An Ultralow Jitter Fractional-N PLL Enabled by an Intrinsically Linear Variable-Slope SPD for QE Cancellation

An Ultralow Jitter Fractional-N PLL Enabled by an Intrinsically Linear Variable-Slope SPD for QE Cancellation 150 150
Author(s): Yanchao Liu, Kaihang Wang, Yang Li, Xiaohua Yu, Ronghua Ni

Abstract:

This article presents a high-performance 13.2-GHz fractional-N sampling phase-locked loop (PLL). To overcome the nonlinearity bottlenecks inherent in edge-restoring buffers used in conventional digital-to-time converters (DTCs), an intrinsically linear variable-slope sampling phase detector (VS-SPD) is proposed. By seamlessly merging an RC delay network with a sampling phase detector (SPD), the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3735859
Publisher: IEEE

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