Timing

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An 18.4-Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using Four-Phase Hybrid Timing Alignment and Dual Equalization

An 18.4-Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using Four-Phase Hybrid Timing Alignment and Dual Equalization 150 150
Author(s): Minchang Kim, Hankyu Chi, Sooncheol Kwon, Icsu Oh, Seulgi Kim, Heewoong Song, Daeho Yun, Jaehong Jeong, Daejoon Kim, Kichul Hong, Jeonghyun Park, Woo-Seok Choi, Hae-Kang Jung, Hoyoung Son, Inchul Jeong, Hyungsoo Kim, Jonghwan Kim

Abstract:

This letter presents a simultaneous bidirectional (SBD) transceiver for post HBM4. It is difficult to increase the data rate due to poor channel characteristics of the silicon interposer and the limited physical area of the IO in high-bandwidth memory (HBM) interface. SBD signaling is attractive because it doubles the per-pin …

Published in: IEEE Solid-State Circuits Letters
Page(s): 182 – 185
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3696268
Publisher: IEEE

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A 6-Bit Serializer with Integrated Manchester Encoder Using Flexible a-IGZO TFT Technology

A 6-Bit Serializer with Integrated Manchester Encoder Using Flexible a-IGZO TFT Technology 150 150
Author(s): Suyash Shrivastava, Pydi Ganga Bahubalindruni

Abstract:

This manuscript presents an experimental characterization of a novel 6-bit parallel-to-serial data converter integrated with Manchester encoder. The system comprises of an on-chip digital logic block that generates six mutually non-overlapping control signals (ϕ0−5) and three 120° phase-shifted clock signals to drive the switching transistors in the serializer and the Manchester encoder (…

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3707465
Publisher: IEEE

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Open DRAM Model Part II: Enabling Processing-in-Memory in 3D DRAM

Open DRAM Model Part II: Enabling Processing-in-Memory in 3D DRAM 150 150
Author(s): Kiseok Lee, Seongkwang Lim, Suman Datta, Shimeng Yu

Abstract:

Processing-in-memory (PIM) by implementing Boolean logic function in DRAM has been proposed to alleviate the memory wall problem in data-intensive computing. However, quantitatively evaluating DRAM-based logic operations across different DRAM architectures remains challenging due to the lack of publicly available DRAM cell and peripheral transistor models that accurately capture their …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704508
Publisher: IEEE

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P-Dits for the Frequency Assignment Problem With Transmitter Deactivation in Dense Environments

P-Dits for the Frequency Assignment Problem With Transmitter Deactivation in Dense Environments 150 150
Author(s): Christian Duffee, Jordan Athas, Igor Kadota, Randall Berry, Pedram Khalili Amiri

Abstract:

The frequency assignment problem is a nondeterministic polynomial-time hard (NP-hard) optimization problem concerning the assignment of frequency channels to wireless transmitters. Typically, the aim is to minimize interference between transmitters while maintaining a high level of service. In this work, the use of probabilistic d-dimensional bits, or p-dits, for this …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 78 – 85
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3690563
Publisher: IEEE

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A −248-dB FOMref CS-Fusion PLL Architecture Combining the Advantages of PFD-CP PLLs and Sampling PLLs in a Single Loop

A −248-dB FOMref CS-Fusion PLL Architecture Combining the Advantages of PFD-CP PLLs and Sampling PLLs in a Single Loop 150 150
Author(s): Junyuan Su, Yuxuan Hu, Zherui Zhang, Lei Wang, Yuncai Zhuang, Fei Song, Jiayoon Ru

Abstract:

This article introduces a CP-sampling (CS)-fusion PLL architecture that combines the advantages of PFD-CP PLLs (robust and speedy locking) and sampling PLLs (low jitter/power) in a single loop. The PFD sends pulsewidth-modulation (PWM) pulses to a merged $mathbf {G_{m}}$ /CP (GCP) block so that the phase error …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 20
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3704989
Publisher: IEEE

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A Bio-Impedance Readout IC With Phase-Locked Sampling for Real-Time Electrical Impedance Spectroscopy

A Bio-Impedance Readout IC With Phase-Locked Sampling for Real-Time Electrical Impedance Spectroscopy 150 150
Author(s): Seonghyun Park, Song-I Cheon, Haidam Choi, Sein Oh, Sohmyung Ha, Minkyu Je

Abstract:

This article presents an electrical bio-impedance (bioZ) spectroscopy integrated circuit (IC) that achieves both high-throughput and high-accuracy. The proposed phase-locked sampling (PLS) scheme, which employs a sampling phase-locked loop (SPLL) and a reference resistor ( $R_{\textit {REF}}$ ), enables fast and precise impedance demodulation. By extracting the impedance components through sampling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3704052
Publisher: IEEE

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A Single-Lead ECG Wearable Sensor With 1.04 s Latency for Cardiac and Biometric Detection Tasks

A Single-Lead ECG Wearable Sensor With 1.04 s Latency for Cardiac and Biometric Detection Tasks 150 150
Author(s): Yuxin Ji, Chao Wang, Yuzhi Hao, Yang Zhao, Jian Zhao, Mingyi Chen, Guoxing Wang, Yong Lian, Yongfu Li

Abstract:

The wearable electrocardiogram (ECG) sensor has immense potential for cardiovascular healthcare monitoring. However, uploading ECG signals to server-side devices for diagnosis poses privacy risks. Multi-tasking ECG processors rely on multi-beat windows and complex models, leading to high latency and energy consumption that limit deployment in resource-constrained wearable devices. In this …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3700263
Publisher: IEEE

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An Incremental Noise-Shaping Pipeline ADC With Single-Amplification-Based kT/C Noise Cancellation Technique

An Incremental Noise-Shaping Pipeline ADC With Single-Amplification-Based kT/C Noise Cancellation Technique 150 150
Author(s): Zongnan Wang, Bingrui Li, Jiajun Tang, Zhongyi Wu, Haoyang Luo, Yuan Wang, Xiyuan Tang

Abstract:

This article presents an incremental noise-shaping (NS) pipeline analog-to-digital converter (ADC) featuring a single-amplification-based kT/C noise cancellation technique. By pre-amplifying the frontend sampling kT/C noise onto the capacitive digital-to-analog converter (CDAC) of the backend NS successive approximation register (SAR) quantizer, the proposed architecture eliminates the repeated amplifications typically …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3698875
Publisher: IEEE

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A Ka-Band Time-Modulated Phase-Invariant Variable-Gain Amplifier With 30-dB Gain Tuning Based on Duty-Cycle Control

A Ka-Band Time-Modulated Phase-Invariant Variable-Gain Amplifier With 30-dB Gain Tuning Based on Duty-Cycle Control 150 150
Author(s): Dongfan Xu, Minzhe Tang, Haiyun Gu, Yuxuan Liu, Yilun Chen, Ziyuan Ren, Minghao Fan, Daxu Zhang, Yi Zhang, Duo Li, Zheng Li, Zezheng Liu, Chun Wang, Yudai Yamazaki, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a time-modulated variable-gain amplifier (VGA) employing a clock-sampling topology governed by a duty-cycle control (DCC) loop. By modulating the effective operation time of the amplifier rather than altering its RF bias conditions, for precise tuning of the clock duty cycle, enabling phase consistency at millimeter-wave frequencies. The …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3695362
Publisher: IEEE

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