Throughput

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A 28-nm 18.7 TOPS/mm $^2$ 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh
A 28-nm 18.7 TOPS/mm $^2$ 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh 150 150
Author(s): Yi Zhan, Wei-Han Yu, Ka-Fai Un, Rui P. Martins, Pui-In Mak

Abstract:

This article reports a high-density 3T1C single-finger (SF) embedded dynamic random access memory (eDRAM) compute-in-memory (CIM) macro. It features several techniques that enhance the memory density, the energy efficiency, and the throughput density, namely: 1) a high-density 3T1C SF-eDRAM cell with low-leakage retention (LLR) to improve the memory density …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3387995
Publisher: IEEE

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A 2 $\times$ 56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS
A 2 $\times$ 56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS 150 150
Author(s): Liping Zhong, Hongzhi Wu, Weitao Wu, Catherine Wang, Wenbo Xiao, Xiongshi Luo, Yangyi Zhang, Dongfan Xu, Wei Wang, Taiyang Fan, Zhenghao Li, Xuxu Cheng, Quan Pan

Abstract:

A 2 $times$ 56 Gb/s 0.78-pJ/b four pulse-amplitude modulation (PAM-4) single-ended multiple-input multiple-output (MIMO) crosstalk cancellation and signal reutilization (XTCR) receiver (RX) is investigated for medium-reach (MR) backplane communications. An XTCR scheme based on active crosstalk extraction (A-XTCR) is proposed to improve the signal reutilization efficiency of the RX. By …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3387355
Publisher: IEEE

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PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs
PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs 150 150
Author(s): Amitesh Sridharan, Jyotishman Saikia, Anupreetham, Fan Zhang, Jae-Sun Seo, Deliang Fan

Abstract:

We present a fully digital multiply and accumulate (MAC) in-memory computing (IMC) macro demonstrating one of the fastest flexible precision integer-based MACs to date. The design boasts a new bit-parallel architecture enabled by a 10T bit-cell capable of four AND operations and a decomposed precision data flow that decreases the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 102 – 105
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3369058
Publisher: IEEE

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