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An Extendable Wideband Band-Divided SPnT Switch Topology Based on a Reconfigurable Pole-to-Throw Network

An Extendable Wideband Band-Divided SPnT Switch Topology Based on a Reconfigurable Pole-to-Throw Network 150 150
Author(s): Zhaowu Wang, Hao Ning, Xinyan Li, Ze Yu, Qiliang Li, Xiaochen Tang, Yong Wang

Abstract:

This article presents an extendable wideband band-divided SP $n$ T switch topology based on a reconfigurable pole-to-throw network (RPTN). Compared to conventions, it mitigates the loss degradation resulting from complex signal routing in advanced RF front-ends. This is enabled by the RPTN, which divides the throws into low-/mid-/high-band (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3711644
Publisher: IEEE

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A Performance Comparison Between W-Band Sequential and Doherty Power Amplifiers for Power Back-Off Efficiency Improvement

A Performance Comparison Between W-Band Sequential and Doherty Power Amplifiers for Power Back-Off Efficiency Improvement 150 150
Author(s): Yahia Ibrahim, Ali M. Niknejad

Abstract:

This work presents a W-band sequential power amplifier (PA) featuring a compact and low-loss output combiner that enhances power back-off (PBO) efficiency by combining a main PA and an auxiliary PA through an isolated combining output network. The proposed architecture is analyzed and experimentally compared to the conventional Doherty PA (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3708783
Publisher: IEEE

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A Low-Spur Fractional-N DPLL With Analog Pre-Distortion DTC Implementing Second-/Third-Order Calibration

A Low-Spur Fractional-N DPLL With Analog Pre-Distortion DTC Implementing Second-/Third-Order Calibration 150 150
Author(s): Daxu Zhang, Yuncheng Zhang, Dingxin Xu, Hongye Huang, Waleed Madany, Zezheng Liu, Wenqian Wang, Yuang Xiong, Ashbir Aviat Fadila, Duo Li, Minzhe Tang, Dongfan Xu, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a low-spur, low-jitter fractional-N digital phase-locked loop (DPLL) employing an analog pre-distortion digital-to-time converter (APD-DTC) to suppress fractional spurs by compensating for both second- and third-order nonlinearities without using complex digital pre-distortion. To support background calibration, a spur-level detection scheme using phase detector gain (PDG) is proposed …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3706350
Publisher: IEEE

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A Ka-Band Time-Modulated Phase-Invariant Variable-Gain Amplifier With 30-dB Gain Tuning Based on Duty-Cycle Control

A Ka-Band Time-Modulated Phase-Invariant Variable-Gain Amplifier With 30-dB Gain Tuning Based on Duty-Cycle Control 150 150
Author(s): Dongfan Xu, Minzhe Tang, Haiyun Gu, Yuxuan Liu, Yilun Chen, Ziyuan Ren, Minghao Fan, Daxu Zhang, Yi Zhang, Duo Li, Zheng Li, Zezheng Liu, Chun Wang, Yudai Yamazaki, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a time-modulated variable-gain amplifier (VGA) employing a clock-sampling topology governed by a duty-cycle control (DCC) loop. By modulating the effective operation time of the amplifier rather than altering its RF bias conditions, for precise tuning of the clock duty cycle, enabling phase consistency at millimeter-wave frequencies. The …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3695362
Publisher: IEEE

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