Text-to-motion models are AI systems that generate human motion sequences directly from natural language descriptions, serving as key enablers for immersive virtual avatars and interactive digital humans in AR/VR ecosystems. However, state-of-the-art text-to-motion diffusion models suffer from substantial computational costs due to their iterative nature, making them ill-suited for …
This letter presents a 3-D Gaussian rendering processor that integrates a spherical beta (SB) illumination module with a mixed-precision rendering engine to enable energy-efficient novel-view synthesis on edge devices. SB replaces spherical harmonics (SH) with a hardware-efficient kernel implemented using a pipelined fixed-point piecewise linear (PWL) power unit. The pipeline …
This work presents a digital-to-time converter (DTC)-based fractional-N digital phase-locked loop (PLL) designed to achieve simultaneously low jitter and low spurs. We introduce a novel DTC chopping technique that effectively mitigates fractional spurs, which we identify as predominantly arising from even-order nonlinearity invariable-slope (VS) DTCs. The proposed technique suppresses …
This work proposed a multiplexer-based neural network (MUXnet), a multiplexer-based, multiplier-free neural network (NN) structure applicable to the implementation of all inner product-based NN layers. An on-chip MUXnet-based neural signal processing unit (NSPU) was designed, achieving a state-of-the-art accuracy of 82.4% on a public human sleep staging dataset, with the lowest …
This letter presents a 14-bit 500-MS/s 3-stage pipelined successive approximation register (SAR) analog-to-digital converter (ADC). By exploiting robust 2b/cycle SAR ADCs, this ADC incorporates significant voltage and time redundancy. High SFDR is achieved through several linearity enhancement techniques. First, a DAC splitting technique addresses the common-mode voltage matching …
This letter presents a flexible and energy-efficient RISC-V system-on-chip (SoC) in 22nm FinFET technology, achieving state-of-the-art performance by tightly integrating the CPU with a synthesized embedded FPGA (embedded field programmable gate array (eFPGA)), enabling the implementation of reconfigurable custom instructions. The tight integration of the eFPGA with SoC scratchpad memory …
