system-on-chip (SoC)

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A Runtime Reconfigurable Array (RTRA) for Multiprogram ML and DSP Acceleration With Hierarchical Partitioning and On-Chip Multilevel Scheduling

A Runtime Reconfigurable Array (RTRA) for Multiprogram ML and DSP Acceleration With Hierarchical Partitioning and On-Chip Multilevel Scheduling 150 150
Author(s): Hongseok Lee, Jack Burd, Tim Ling, Yao-Kai Yang, Nian-Shyang Chang, Wen-Ching Chen, Chi-Shi Chen, Tzi-Dar Chiueh, Michael Kuan-Tse Lee, Chia-Hsiang Yang, Dejan Marković

Abstract:

Emerging applications with highly dynamic digital signal processing (DSP) and machine-learning (ML) workloads demand a hardware platforms that simultaneously deliver high performance, high energy efficiency, and low-latency reconfiguration. Such systems must adapt to evolving algorithms, variable data rates, and multiprogram tenancy without incurring prohibitive switching overhead. The conventional reconfigurable architectures …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5296 – 5312
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715500
Publisher: IEEE

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Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data

Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data 150 150
Author(s): Douwe den Blanken, Charlotte Frenkel

Abstract:

On-device learning at the edge enables low-latency, private personalization with improved long-term robustness and reduced maintenance costs. Yet, achieving scalable, low-power (LP) end-to-end on-chip learning, especially from real-world sequential data with a limited number of examples, is an open challenge. Indeed, accelerators supporting error backpropagation optimize for learning performance at …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3645640
Publisher: IEEE

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kNOT: A 2-D Distributed Network-on-Textile Architecture With Direct Die-to-Yarn Integration of 0.6 × 2.15 mm2 SoC and bySPI Chiplets for Wearable Computing

kNOT: A 2-D Distributed Network-on-Textile Architecture With Direct Die-to-Yarn Integration of 0.6 × 2.15 mm2 SoC and bySPI Chiplets for Wearable Computing 150 150
Author(s): Anjali Agrawal, Zhenghong Chen, Braden E. Desman, Jinhua Wang, Akiyoshi Tanaka, Fahim Foysal, Charles D. Hess, Will Farrell, Jim Owens, Daniel S. Truesdell, Benton H. Calhoun

Abstract:

This article presents kNOT, a scalable, distributed, and 2-D Network-On-Textile (kNOT) comprising miniaturized systems on chip (SoCs) and bypass SPI (bySPI) networking chiplets that together enable diverse networking and computational tasks. To preserve garment comfort and flexibility, kNOT eliminates bulky boards and interposers through direct-die attachment to embroidered yarns. The …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 103 – 115
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3624099
Publisher: IEEE

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A RISC-V SoC With Reconfigurable Custom Instructions on a Synthesized eFPGA Fabric in 22nm FinFET

A RISC-V SoC With Reconfigurable Custom Instructions on a Synthesized eFPGA Fabric in 22nm FinFET 150 150
Author(s): Prashanth Mohan, Siddharth Das, Ken Mai

Abstract:

This letter presents a flexible and energy-efficient RISC-V system-on-chip (SoC) in 22nm FinFET technology, achieving state-of-the-art performance by tightly integrating the CPU with a synthesized embedded FPGA (embedded field programmable gate array (eFPGA)), enabling the implementation of reconfigurable custom instructions. The tight integration of the eFPGA with SoC scratchpad memory …

Published in: IEEE Solid-State Circuits Letters
Page(s): 321 – 324
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3618942
Publisher: IEEE

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