Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile One-Bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference https://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg 150 150 https://secure.gravatar.com/avatar/8fcdccb598784519a6037b6f80b02dee03caa773fc8d223c13bfce179d70f915?s=96&d=mm&r=g
Abstract:
Spin-transfer-torque magnetic random-access memory (STT-MRAM) is attractive for nonvolatile one-bit sign-weight storage, but a favorable cell or local-read metric does not establish subsystem efficiency. We analyze a hybrid magnetic tunnel junction (MTJ)–complementary metal-oxide-semiconductor (CMOS) memory subsystem in which MTJs store static signs while sensing, reference generation, sign staging, scale …