static random access memory (SRAM)

A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm2-17 TFLOPS/mm2 SRAM-Based INT8, and FP16 Digital-CIM Compiler With Support for Multi-Weight Update/Cycle

A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm2-17 TFLOPS/mm2 SRAM-Based INT8, and FP16 Digital-CIM Compiler With Support for Multi-Weight Update/Cycle 150 150

Abstract:

This article presents an static random-access memory (SRAM)-based digital compute-in-memory (CIM) compiler implemented with 3 nm high- $\kappa $ metal gate (HKMG) FinFET technology, supporting flexible INT8 and FP16 formats for weight and activation multiply-accumulate (MAC) operations, offering configuration flexibility, high accuracy, and improved area and power efficiency. The FP16 digital …

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A High-Density Low-Leakage and Low-Power Fully Voltage-Stacked SRAM for IoT Application

A High-Density Low-Leakage and Low-Power Fully Voltage-Stacked SRAM for IoT Application 150 150

Abstract:

The general approach to suppress leakage in static random access memory (SRAM) is to use a low voltage ( $V_{text {L}}$ ), generated by a low-dropout regulator (LDO), as the cell supply voltage (CVDD) of SRAM array in the standby mode. However, the effectiveness of lowering CVDD is constrained by the …

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