Specific absorption rate

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A 12b 180MS/s Pipelined-SAR ADC with a Low-Power Calibration-Free RA and Hardware-Efficient SAR Logic

A 12b 180MS/s Pipelined-SAR ADC with a Low-Power Calibration-Free RA and Hardware-Efficient SAR Logic 150 150
Author(s): Guo Wei, Rui Zhang, Fule Li, Hanjun Jiang, Zhihua Wang

Abstract:

This letter presents a 12-bit 180-MS/s pipelined-SAR ADC in 65-nm CMOS. To eliminate the complex interstage gain-error calibration for fast-response characteristic, a high-gain residue amplifier (RA) featuring a 2-stage gain-boosting architecture is proposed. By removing the tail current, the RA significantly alleviates slew-rate and voltage headroom limitations. The pre-amplifier …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697220
Publisher: IEEE

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A Zero-Static-Power ADC with Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR from -40 °C to 85 °C

A Zero-Static-Power ADC with Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR from -40 °C to 85 °C 150 150
Author(s): Yiming Wang, Yihang Luan, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents a 10-bit ENOB charge-sharing SAR ADC with a fully integrated dynamic bandgap reference (BGR), enabling first-order noise shaping and ultra-low-power operation. The charge-sharing ADC and dynamic BGR form an ideal pair: both operate without static current, allowing compact integration and high precision. The SAR uses only three …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697203
Publisher: IEEE

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A 77-dB DR Two-Stage SAR ADC for Low-Gain Analog Front-Ends Using Asynchronous Pipelining and RC Snubber Reference Stabilization

A 77-dB DR Two-Stage SAR ADC for Low-Gain Analog Front-Ends Using Asynchronous Pipelining and RC Snubber Reference Stabilization 150 150
Author(s): Jun Feng, Rares Bodnar, Roberto Maurino, Marcel J. M. Pelgrom, Filip Tavernier

Abstract:

The analog front-end (AFE) often bottlenecks the power of modern receiver chains, burdened by the large-signal linearity required before the ADC. This work introduces a 77-dB DR, 200-MS/s two-stage SAR ADC that can alleviate much of this burden by offering a significantly lower input-referred noise (IRN) to enable low-gain …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3686660
Publisher: IEEE

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