Solid state circuits

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PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI

PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI 150 150
Author(s): Jakob Finkbeiner, Raphael Nägele, Manuel Wittlinger, Markus Grözing, Manfred Berroth, Georg Rademacher

Abstract:

Analog computing offers intrinsic energy and latency benefits that makes it attractive for real-time and edge applications. Conventional analog accelerators suffer from repeated conversions between analog and digital domain, which degrades efficiency and throughput. We propose an all-analog pipelined neural network accelerator architecture in 22 nm fully-depleted silicon-on-insulator (FD-SOI) complementary metal-oxide-semiconductor (…

Published in: IEEE Solid-State Circuits Letters
Page(s): 365 – 368
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3627274
Publisher: IEEE

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An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration

An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration 150 150
Author(s): Changjoo Kim, Sooho Park, Yohan Choi, Minkyun Shim, Woojin Lee, Donghwi Seo, Chulwoo Kim

Abstract:

This letter presents an 8-bit 400 MS/s 1-then-2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) employing a comparator rotation-based background offset calibration (CRBC) technique. Unlike conventional 1-then-2-bit/cycle architectures, where calibration validity depends on the input voltage, the proposed comparator rotation-based background calibration enables input-independent background calibration, …

Published in: IEEE Solid-State Circuits Letters
Page(s): 345 – 348
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3624263
Publisher: IEEE

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3D-IC Chiplet Integrated Power Supply With LDO, SCVR, and Buck DC–DC Converter

3D-IC Chiplet Integrated Power Supply With LDO, SCVR, and Buck DC–DC Converter 150 150
Author(s): Xiaosen Liu, Xichen Sun, Renwei Chen, Haozhe Zhang, Zhoutong Liu, Yan Wang

Abstract:

With the rapid advancement of chiplet and heterogenous integration technologies, delivering power through the package, redistribution layer (RDL), and chip layers in 3-D space has become a fundamental challenge for high-performance SoCs. This letter provides a comprehensive overview of power delivery solutions, including low-dropout regulator (LDOs), switched capacitor converters, and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 341 – 344
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3624096
Publisher: IEEE

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A Wideband Calibration-Free D-Band Passive Phase Shifter With Frequency-Invariant Codes Over 24% Fractional Bandwidth

A Wideband Calibration-Free D-Band Passive Phase Shifter With Frequency-Invariant Codes Over 24% Fractional Bandwidth 150 150
Author(s): Basem Abdelaziz Abdelmagid, Yuqi Liu, Hua Wang

Abstract:

This work presents a compact 110–140 GHz bidirectional D-band passive phase shifter based on combining a 5-stage capacitively-loaded reflective-type PS (RTPS) with a wideband 0°/180° stage. The design achieves a 360° phase range with a resolution of 11.25°. By applying: 1) a wideband RTPS design methodology on the stage level; 2) frequency/switching-staggering techniques among the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 329 – 332
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3622233
Publisher: IEEE

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Dual-Junction Monolithically Integrated Monitoring Photodiode With a Two-Stage 18 GHz 18 pA/√Hz TIA in 22-nm FDSOI

Dual-Junction Monolithically Integrated Monitoring Photodiode With a Two-Stage 18 GHz 18 pA/√Hz TIA in 22-nm FDSOI 150 150
Author(s): Jelle H. T. Bakker, Nimit Jain, Paul Klatser, Mark S. Oude Alink, Bram Nauta

Abstract:

We present a monolithically integrated (MI) dualjunction monitoring photodiode (PD) and transimpedance amplifier (TIA). The photocurrent originates from the deep Nwell (DNW)/P-type substrate (PSUB) $({\lt }5~ \mathrm {GHz})$ and the P-Well $(\mathrm {PW}) / \mathrm {DNW}({\gt }1~ \mathrm {GHz})$ junctions. The presented combination of bulk PD and 22 nm fully-depleted silicon-on-insulator (FDSOI) …

Published in: IEEE Solid-State Circuits Letters
Page(s): 313 – 316
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3615656
Publisher: IEEE

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A 40.68-MHz, 200-ns-Settling Active Rectifier for mm-Sized Implants

A 40.68-MHz, 200-ns-Settling Active Rectifier for mm-Sized Implants 150 150
Author(s): Ronald Wijermars, Yi-Han Ou-Yang, Sijun Du, Dante G. Muratore

Abstract:

This letter describes a fast-settling active rectifier for a 40.68 MHz wireless power transfer receiver for implantable applications. Fast-settling and low power are achieved through a novel direct voltage-domain compensation technique. The rectifier maintains high efficiency during load and link variations required for downlink communication. The system was fabricated in 40nm …

Published in: IEEE Solid-State Circuits Letters
Page(s): 305 – 308
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3611484
Publisher: IEEE

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24.86 Gb/s Full-Digital Chaos Random Number 1.53 GSamples/s Noise Generator in 40nm CMOS

24.86 Gb/s Full-Digital Chaos Random Number 1.53 GSamples/s Noise Generator in 40nm CMOS 150 150
Author(s): Cheng-Bin Chen, Tsung Chen, Yuan-Hao Huang

Abstract:

This letter presents a fully digital true random number generator (TRNG) and noise generator (NG) based on a chaos system. We design the chaos random number generator (CRNG) using the proposed Euler-based modified Lorenz system with periodic perturbation and modified modulo unit. The chaos NG (CNG) processor integrates the CRNG …

Published in: IEEE Solid-State Circuits Letters
Page(s): 253 – 256
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3605369
Publisher: IEEE

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A 0-to- 10μF Off-Chip Output Capacitor-Scalable Boost Converter Achieving 96.68% Peak Efficiency

A 0-to- 10μF Off-Chip Output Capacitor-Scalable Boost Converter Achieving 96.68% Peak Efficiency 150 150
Author(s): Hyeon-Ji Choi, Joo-Mi Cho, Hyo-Jin Park, Seok-Jun Lee, Sung-Wan Hong

Abstract:

This letter presents an off-chip output capacitor (CO)-scalable (OCS) boost converter. The proposed OCS boost converter is possible to operate both with and without the off-chip CO. In addition, it operates in a whole conversion ratio (CR) range over 1 while maintaining a small current ripple of an inductor, resulting …

Published in: IEEE Solid-State Circuits Letters
Page(s): 233 – 236
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3594739
Publisher: IEEE

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Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency

Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency 150 150
Author(s): Yichen Xu, Zhaoqing Wang, Rentao Wan, Suhwan Kim, Minxiang Gong, Ram Krishnamurthy, Xin Zhang, Mingoo Seok

Abstract:

This paper proposes a digital low-dropout regulator (DLDO)-assisted buck converter featuring one-step computational droop compensation and DLDO feedback-controlled current handover. The 28-nm test chip achieves a 68-mV droop voltage and a 112-ns settling time for a 1A/0.8ns load step while maintaining a high peak efficiency of 95.5%.

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3581844
Publisher: IEEE

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