Corrections to “A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array”https://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg150150https://secure.gravatar.com/avatar/8935a7dcd6741d8e23d45bb15c1470a8?s=96&d=mm&r=g
A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6-GHz Bandwidth, 2.7-pA/Hz0.5 Input-Referred Noise, and 103-dBΩ Transimpedance Gainhttps://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg150150https://secure.gravatar.com/avatar/8935a7dcd6741d8e23d45bb15c1470a8?s=96&d=mm&r=g
Author(s): Zhao Zhang, Yidan Zhang, Yiqing Xu, Xinyu Shen, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
Abstract:
This letter presents a low-noise wideband analog front-end (AFE) circuit for long-range linear LiDAR. The nMOS feedforward transimpedance amplifier with inner feedback resistor (NFFR-TIA) is proposed to extend the bandwidth to around 400 MHz and reduce the input referred noise (IRN) concurrently with high-transimpedance gain and improved stability. Two stage continuous-time …
Published in: IEEE Solid-State Circuits Letters
Page(s): 131 – 134
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3378093
Publisher: IEEE
A 6.4-Gb/s/pin nand Flash Memory Multichip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systemshttps://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg150150https://secure.gravatar.com/avatar/8935a7dcd6741d8e23d45bb15c1470a8?s=96&d=mm&r=g
This letter describes a NAND flash memory multichip package (NAND MCP) incorporating a developed LSI interface (IF) Chip (Bridge Chip) in which the IF to and from the solid-state drive (SSD) controller has twice the speed as that of the IF to and from the NAND dies even with multiple …
Published in: IEEE Solid-State Circuits Letters
Page(s): 115 – 118
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3377263
Publisher: IEEE
A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Arrayhttps://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg150150https://secure.gravatar.com/avatar/8935a7dcd6741d8e23d45bb15c1470a8?s=96&d=mm&r=g
Analog computing-in-memory (CIM) using emerging resistive nonvolatile memory (NVM) technologies faces challenges, such as static power consumption, current flow-induced IR drop, and the need for multiple power-hungry ADCs. In this letter, we present ferroelectric capacitive array (FCA)-based energy/area-efficient CIM macro used for charge-domain multiply-and-accumulate operations, which addresses the …
Published in: IEEE Solid-State Circuits Letters
Page(s): 70 – 73
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3361011
Publisher: IEEE