Solid state circuits

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Corrections to “A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array”

Corrections to “A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array” 150 150
Author(s): Injune Yeo, Wangxin He, Yuan-Chun Luo, Shimeng Yu, Jae-Sun Seo

Abstract:

In the article [1], Table 2 was incorrectly copied from Table I. The correct Table 2 in [1] is shown below.

Published in: IEEE Solid-State Circuits Letters
Page(s): 110 – 110
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3371728
Publisher: IEEE

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A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6-GHz Bandwidth, 2.7-pA/Hz0.5 Input-Referred Noise, and 103-dBΩ Transimpedance Gain

A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6-GHz Bandwidth, 2.7-pA/Hz0.5 Input-Referred Noise, and 103-dBΩ Transimpedance Gain 150 150
Author(s): Zhao Zhang, Yidan Zhang, Yiqing Xu, Xinyu Shen, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu

Abstract:

This letter presents a low-noise wideband analog front-end (AFE) circuit for long-range linear LiDAR. The nMOS feedforward transimpedance amplifier with inner feedback resistor (NFFR-TIA) is proposed to extend the bandwidth to around 400 MHz and reduce the input referred noise (IRN) concurrently with high-transimpedance gain and improved stability. Two stage continuous-time …

Published in: IEEE Solid-State Circuits Letters
Page(s): 131 – 134
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3378093
Publisher: IEEE

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A 6.4-Gb/s/pin nand Flash Memory Multichip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems

A 6.4-Gb/s/pin nand Flash Memory Multichip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems 150 150
Author(s): Shinichi Ikeda, Akira Iwata, Goichi Otomo, Tomoaki Suzuki, Hiroaki Iijima, Mikio Shiraishi, Shinya Kawakami, Masatomo Eimitsu, Yoshiki Matsuoka, Kiyohito Sato, Shigehiro Tsuchiya, Yoshinori Shigeta, Takuma Aoyama

Abstract:

This letter describes a NAND flash memory multichip package (NAND MCP) incorporating a developed LSI interface (IF) Chip (Bridge Chip) in which the IF to and from the solid-state drive (SSD) controller has twice the speed as that of the IF to and from the NAND dies even with multiple …

Published in: IEEE Solid-State Circuits Letters
Page(s): 115 – 118
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3377263
Publisher: IEEE

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A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array

A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array 150 150
Author(s): Injune Yeo, Wangxin He, Yuan-Chun Luo, Shimeng Yu, Jae-Sun Seo

Abstract:

Analog computing-in-memory (CIM) using emerging resistive nonvolatile memory (NVM) technologies faces challenges, such as static power consumption, current flow-induced IR drop, and the need for multiple power-hungry ADCs. In this letter, we present ferroelectric capacitive array (FCA)-based energy/area-efficient CIM macro used for charge-domain multiply-and-accumulate operations, which addresses the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 70 – 73
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3361011
Publisher: IEEE

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