Solid state circuits

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Birch: A Real-Time Multi-Domain Multi-Task Extended Reality Perception Accelerator

Birch: A Real-Time Multi-Domain Multi-Task Extended Reality Perception Accelerator 150 150
Author(s): Kathleen Feng, Kai Bartolone, Kartik Prabhu, Brianna McColm, Xingyu Ni, Siddhant Gupta, Priyanka Raina

Abstract:

Birch is a system-on-chip that efficiently and accurately accelerates the multi-task multi-domain extended reality (XR) perception pipeline, with workloads such as visual inertial odometry (VIO), eye gaze tracking, and scene understanding. Birch features vision modules with cascaded line buffers, in-step feature sorting, and double-buffered optical flow to extract and track …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3673168
Publisher: IEEE

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A 7-level 18-wire-state Trio-signaling Transmitter for MIPI C-PHY 3.0 Interfaces

A 7-level 18-wire-state Trio-signaling Transmitter for MIPI C-PHY 3.0 Interfaces 150 150
Author(s): Junyeong Lee, Myeongjin Oh, Kiwoon Kim, Jung-Hoon Chun

Abstract:

This paper presents a MIPI C-PHY v3.0 TX, which adopts trio-signaling using three wires per lane. Each line supports 7-level signaling, enabling 18 wire states to map 32-bit data into 9 symbols, achieving 3.56 bits/symbol efficiency. Balanced coding maintains constant driver current, enhancing SSO noise immunity, and embedded clocking is achieved by …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3672642
Publisher: IEEE

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A 70-GHz Bandwidth Amplifier With Integrated Differential Bridged T-coil Peaking and Uniform Group Delay

A 70-GHz Bandwidth Amplifier With Integrated Differential Bridged T-coil Peaking and Uniform Group Delay 150 150
Author(s): Giovanni Scarlato, John R. Long

Abstract:

A two-stage amplifier in 22-nm FD-SOI CMOS integrates a fully-differential bridged T-coil for the first time. Circuit performance is benchmarked against an identical amplifier topology designed with single-ended T-coils (pseudo-differential) and an unpeaked reference. It realizes 70-GHz bandwidth with $12~\pm ~2$ -ps group delay and >10-dB return loss across 90 GHz. Bandwidth …

Published in: IEEE Solid-State Circuits Letters
Page(s): 65 – 68
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3661366
Publisher: IEEE

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PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI

PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI 150 150
Author(s): Jakob Finkbeiner, Raphael Nägele, Manuel Wittlinger, Markus Grözing, Manfred Berroth, Georg Rademacher

Abstract:

Analog computing offers intrinsic energy and latency benefits that makes it attractive for real-time and edge applications. Conventional analog accelerators suffer from repeated conversions between analog and digital domain, which degrades efficiency and throughput. We propose an all-analog pipelined neural network accelerator architecture in 22 nm fully-depleted silicon-on-insulator (FD-SOI) complementary metal-oxide-semiconductor (…

Published in: IEEE Solid-State Circuits Letters
Page(s): 365 – 368
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3627274
Publisher: IEEE

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An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration

An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration 150 150
Author(s): Changjoo Kim, Sooho Park, Yohan Choi, Minkyun Shim, Woojin Lee, Donghwi Seo, Chulwoo Kim

Abstract:

This letter presents an 8-bit 400 MS/s 1-then-2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) employing a comparator rotation-based background offset calibration (CRBC) technique. Unlike conventional 1-then-2-bit/cycle architectures, where calibration validity depends on the input voltage, the proposed comparator rotation-based background calibration enables input-independent background calibration, …

Published in: IEEE Solid-State Circuits Letters
Page(s): 345 – 348
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3624263
Publisher: IEEE

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3D-IC Chiplet Integrated Power Supply With LDO, SCVR, and Buck DC–DC Converter

3D-IC Chiplet Integrated Power Supply With LDO, SCVR, and Buck DC–DC Converter 150 150
Author(s): Xiaosen Liu, Xichen Sun, Renwei Chen, Haozhe Zhang, Zhoutong Liu, Yan Wang

Abstract:

With the rapid advancement of chiplet and heterogenous integration technologies, delivering power through the package, redistribution layer (RDL), and chip layers in 3-D space has become a fundamental challenge for high-performance SoCs. This letter provides a comprehensive overview of power delivery solutions, including low-dropout regulator (LDOs), switched capacitor converters, and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 341 – 344
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3624096
Publisher: IEEE

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A Wideband Calibration-Free D-Band Passive Phase Shifter With Frequency-Invariant Codes Over 24% Fractional Bandwidth

A Wideband Calibration-Free D-Band Passive Phase Shifter With Frequency-Invariant Codes Over 24% Fractional Bandwidth 150 150
Author(s): Basem Abdelaziz Abdelmagid, Yuqi Liu, Hua Wang

Abstract:

This work presents a compact 110–140 GHz bidirectional D-band passive phase shifter based on combining a 5-stage capacitively-loaded reflective-type PS (RTPS) with a wideband 0°/180° stage. The design achieves a 360° phase range with a resolution of 11.25°. By applying: 1) a wideband RTPS design methodology on the stage level; 2) frequency/switching-staggering techniques among the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 329 – 332
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3622233
Publisher: IEEE

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Dual-Junction Monolithically Integrated Monitoring Photodiode With a Two-Stage 18 GHz 18 pA/√Hz TIA in 22-nm FDSOI

Dual-Junction Monolithically Integrated Monitoring Photodiode With a Two-Stage 18 GHz 18 pA/√Hz TIA in 22-nm FDSOI 150 150
Author(s): Jelle H. T. Bakker, Nimit Jain, Paul Klatser, Mark S. Oude Alink, Bram Nauta

Abstract:

We present a monolithically integrated (MI) dualjunction monitoring photodiode (PD) and transimpedance amplifier (TIA). The photocurrent originates from the deep Nwell (DNW)/P-type substrate (PSUB) $({\lt }5~ \mathrm {GHz})$ and the P-Well $(\mathrm {PW}) / \mathrm {DNW}({\gt }1~ \mathrm {GHz})$ junctions. The presented combination of bulk PD and 22 nm fully-depleted silicon-on-insulator (FDSOI) …

Published in: IEEE Solid-State Circuits Letters
Page(s): 313 – 316
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3615656
Publisher: IEEE

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A 40.68-MHz, 200-ns-Settling Active Rectifier for mm-Sized Implants

A 40.68-MHz, 200-ns-Settling Active Rectifier for mm-Sized Implants 150 150
Author(s): Ronald Wijermars, Yi-Han Ou-Yang, Sijun Du, Dante G. Muratore

Abstract:

This letter describes a fast-settling active rectifier for a 40.68 MHz wireless power transfer receiver for implantable applications. Fast-settling and low power are achieved through a novel direct voltage-domain compensation technique. The rectifier maintains high efficiency during load and link variations required for downlink communication. The system was fabricated in 40nm …

Published in: IEEE Solid-State Circuits Letters
Page(s): 305 – 308
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3611484
Publisher: IEEE

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