Silicon

  • No Comments

Xiling: Cryo-CMOS Manipulator Using Dual 18-bit R-2R DACs for Single-Electron Transistor at 60 mK

Xiling: Cryo-CMOS Manipulator Using Dual 18-bit R-2R DACs for Single-Electron Transistor at 60 mK 150 150
Author(s): Yingjie Li, Yifei Zhang, Haichuan Lin, Cheng Wang

Abstract:

Millions of quantum-bits (qubits) are envisioned for a fault-tolerant quantum computer. For scalability, silicon spin qubit stands out due to its compatibility with advanced CMOS processes. Silicon single-electron transistors (SETs) are widely adopted for the quantum state discrimination of spin qubits. For high-fidelity quantum logic gate and readout, the gate …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3671795
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Standalone-in-Memory Voltage Crossover-Based Assist Switching Circuit for Reliable and Efficient Process Tracking Memory Vmin Improvement in Intel 18A-RibbonFET Technology

A Standalone-in-Memory Voltage Crossover-Based Assist Switching Circuit for Reliable and Efficient Process Tracking Memory Vmin Improvement in Intel 18A-RibbonFET Technology 150 150
Author(s): Saroj Satapathy, Amlan Ghosh, John Riley, Jalal Quadri, Jaydeep Kulkarni, Feroze Merchant

Abstract:

Advanced CMOS memory requires voltage biasing assist techniques to achieve low operating voltages (Vmin), which must be deactivated at higher voltages for high electric field reliability. Centralized power management unit (PMU) control signals face timing synchronization and process tracking challenges when distributed across cores to activate assist circuits in various …

Published in: IEEE Solid-State Circuits Letters
Page(s): 37 – 40
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3652110
Publisher: IEEE

View on IEEE Xplore

  • No Comments

SHINSAI: A 586 mm2 Reusable Active TSV Interposer With Programmable Interconnect Fabric and 512 Mb Underdeck Memory

SHINSAI: A 586 mm2 Reusable Active TSV Interposer With Programmable Interconnect Fabric and 512 Mb Underdeck Memory 150 150
Author(s): Haozhe Zhu, Bo Jiao, Yuman Zeng, Yongjiang Li, Jie Liao, Siyao Jia, Zexing Chen, Liyu Lin, Xuanda Lin, Suchang Huang, Mochen Tian, Jundong Zhu, Dexin Wen, Yan Wang, Yu Wang, Jian Xu, Feng Wang, Jun Tao, Chixiao Chen, Qi Liu, Ming Liu

Abstract:

This article presents SHINSAI—a 586 mm2 reusable active through-silicon via (TSV) interposer addressing key challenges in multi-chiplet integration (MCI) architectures. While active interposers overcome fundamental limitations of passive counterparts by integrating functional circuitry, existing solutions face three critical constraints: 1) non-recurring engineering (NRE) costs from application-specific interposers negating chiplet reuse benefits; 2) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 90 – 102
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3623630
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 37.8 Mb/mm² SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection

A 37.8 Mb/mm² SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection 150 150
Author(s): Harold Pilo, Manish Arora, Chien-An Lai, Mike Lee, Zack Lo, Mayur Randeria

Abstract:

A high-density (HD), SRAM-based register file (RF) has been demonstrated in Intel 18A Technology (Wang et al., 2025 and Pilo et al., 2025) featuring RibbonFET GAA transistors and a back side power delivery network (BSDPN). The RF is optimized for HD and array efficiency and achieves a density of 37.8 Mb/mm2, the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 357 – 360
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3628176
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Non-Volatile ReRAM-Based Compact Event-Triggered Counters

Non-Volatile ReRAM-Based Compact Event-Triggered Counters 150 150
Author(s): Moin Diwan, Shengchao Zhang, Zidu Li, Alex James, Bhaskar Choubey

Abstract:

With an increasing number of transistors per circuit, the fabrication cost and the energy consumption of each integrated circuits increase exponentially, which drives the need to reduce the number of transistors. In this study, we explore a novel design for a 16-bit digital counter that utilizes a combination of complementary …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 131 – 138
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3619415
Publisher: IEEE

View on IEEE Xplore

  • No Comments

An Area and Power Efficient Source Driver IC With Multi-Line Sensing Real-Time Pixel Compensation for OLED Displays

An Area and Power Efficient Source Driver IC With Multi-Line Sensing Real-Time Pixel Compensation for OLED Displays 150 150
Author(s): Jaewoong Ahn, Seung Hun Choi, Minseong Um, Jun Yeol An, Hyung-Min Lee

Abstract:

This article proposes a source driver integrated circuit (SD-IC) with a pixel compensator designed to minimize both silicon area and power consumption for organic light-emitting diode (OLED) displays. The proposed SD-IC is capable of driving ultrahigh-definition (UHD) active-matrix OLED (AMOLED) panels with a one-horizontal-time (1-H time) of $7.2~\mu $ s while …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3614134
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Low-Jitter Fractional-N Digital PLL Using a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial-Based LMS Calibration

A Low-Jitter Fractional-N Digital PLL Using a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial-Based LMS Calibration 150 150
Author(s): Munjae Chae, Seheon Jang, Seungjae Lee, Jaehyouk Choi

Abstract:

This work presents a 10.0–11.5-GHz fractional- $N$ digital phase-locked loop (DPLL) using the quantization-error-compensating bang–bang phase detector (QEC-BBPD) that can minimize both the static delay ( $T_{\mathrm {S}}$ ) and the dynamic delay ( $T_{\mathrm {D}}$ ) required for removing the delta-sigma modulator’s ( $\Delta \Sigma $ M) quantization-error (Q-error). Since the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3611417
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance

A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance 150 150
Author(s): Esteban Garzón, Eyal Rechef, Roman Golman, Odem Harel, Yuval Harary, Paz Snapir, Marco Lanuzza, Adam Teman, Leonid Yavits

Abstract:

The growing need for approximate matching in data-intensive applications, such as data analytics, machine learning, deep learning, and computational genomics has driven the proposal of our Hamming distance (HD) tolerant content-addressable memory (HD-CAM). HD-CAM features a modified NOR-type associative memory cell that leverages the discharge speed of the matchline (ML) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 3009 – 3019
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3529715
Publisher: IEEE

View on IEEE Xplore

Search this website