Sensitivity

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A 54- $\\mu$ W Design-Agnostic Clock, Voltage, and EM-Pulse Fault-Injection Attack Detection Using Time-to-Voltage Conversion

A 54- $\\mu$ W Design-Agnostic Clock, Voltage, and EM-Pulse Fault-Injection Attack Detection Using Time-to-Voltage Conversion 150 150
Author(s): Yudhajit Ray, Archisman Ghosh, Sarthak Antal, Shreyas Sen

Abstract:

This article presents a state-of-the-art design-agnostic clock, voltage, and electromagnetic pulse (EMP)-based fault-injection attack (FIA) detector. The efficient conversion of time-to-voltage information by integrating amplifiers transforms the time anomaly into the voltage domain, enabling its detection at a lower power consumption. The clock-glitch detector design consumes only $53~\mu $ W …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3655593
Publisher: IEEE

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A Compact, Highly-Digital Sensor-Fusion-Based Joint V dd-Temperature Sensor for SoC Thermal Management

A Compact, Highly-Digital Sensor-Fusion-Based Joint V dd-Temperature Sensor for SoC Thermal Management 150 150
Author(s): Hikmet Seha Öztürk, Julian Arenas, Carlos Tokunaga, Nasser Kurd, Visvesh S. Sathe

Abstract:

This article presents a fine-grained thermal sensing network for thermal management in SoCs. Sensor nodes in this network are made up of joint supply voltage ( $V_{\mathrm {dd}}$ ) and temperature ( $T$ ) sensors, which are compact and highly digital. Measurements from these simple but imperfect sensors are jointly processed to extract …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3621280
Publisher: IEEE

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1.58-b FeFET-Based Ternary Neural Networks: Achieving Robust Compute-In-Memory With Weight-Input Transformations

1.58-b FeFET-Based Ternary Neural Networks: Achieving Robust Compute-In-Memory With Weight-Input Transformations 150 150
Author(s): Imtiaz Ahmed, Akul Malhotra, Revanth Koduru, Sumeet Kumar Gupta

Abstract:

Ternary weight neural networks (TWNs), with weights quantized to three states (−1, 0, and 1), have emerged as promising solutions for resource-constrained edge artificial intelligence (AI) platforms due to their high energy efficiency with acceptable inference accuracy. Further energy savings can be achieved with TWN accelerators utilizing techniques such as compute-in-memory (CiM) and …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 157 – 165
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3621160
Publisher: IEEE

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A 48-Gb/s Inductorless PAM-4 Optical Receiver With 1.28-pJ/bit Efficiency in 28-nm CMOS

A 48-Gb/s Inductorless PAM-4 Optical Receiver With 1.28-pJ/bit Efficiency in 28-nm CMOS 150 150
Author(s): Chongyun Zhang, Li Wang, Fuzhan Chen, Quan Pan, Xianbo Li, C. Patrick Yue

Abstract:

This work presents a 48-Gb/s four-level pulse amplitude modulation (PAM-4) optical receiver (ORX) with a linear analog front-end (AFE) and an integrated sampler. The AFE employs a transadmittance-stage transimpedance-stage (TAS-TIS) topology, replacing conventional CML-based variable gain amplifiers (VGAs) and post-amplifiers, avoiding continuous-time linear equalizers and passive inductors while preserving …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3607107
Publisher: IEEE

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A 19.5-GHz Radiation-Hardened Sub-Sampled PLL With Quad-Core VCO in 16-nm FinFET Achieving Sub-50 fs Jitter

A 19.5-GHz Radiation-Hardened Sub-Sampled PLL With Quad-Core VCO in 16-nm FinFET Achieving Sub-50 fs Jitter 150 150
Author(s): David Dolt, Samuel Palermo

Abstract:

This letter presents a radiation-hardened (rad-hard) subsampled phase-locked loop (SS-PLL) that achieves state-of-the-art jitter performance while incorporating radiation-hardened techniques to mitigate single-event-upsets (SEUs) present in the space environment. Furthermore, rad-hard techniques are incorporated in each core PLL subblock which include a rad-hard charge-pump Gm cell, a pulser circuit with triple …

Published in: IEEE Solid-State Circuits Letters
Page(s): 285 – 288
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3610901
Publisher: IEEE

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A 430- μ A 68.2-dB-SNR 133-dBSPL-AOP CMOS-MEMS Digital Microphone Based on Electrostatic Force Feedback Control

A 430- μ A 68.2-dB-SNR 133-dBSPL-AOP CMOS-MEMS Digital Microphone Based on Electrostatic Force Feedback Control 150 150
Author(s): Jiaqi Dong, Qi Zhang, Xinwen Zhang, Yekan Chen, Yili Shen, Bo Zhao, Yuxuan Luo

Abstract:

This article introduces a high-acoustic-dynamic-range and low-power digital microphone based on the electrostatic force feedback control (EFFC). The proposed design adjusts the sensitivity of the micro-electro-mechanical system (MEMS) by adaptively biasing it at different input amplitudes, thereby extending the dynamic range (DR). The proposed adaptive biasing technique allows the induced …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1199 – 1209
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3531509
Publisher: IEEE

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