Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS https://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg 150 150 https://secure.gravatar.com/avatar/8fcdccb598784519a6037b6f80b02dee03caa773fc8d223c13bfce179d70f915?s=96&d=mm&r=g
Abstract:
This article introduces two comparators featuring a dynamic-bias preamplifier and self-clocked latches, tailored for ultra-low-power and medium-speed applications with <500- $\mu $ V input-referred noise (IRN). The proposed self-clocked latches are activated by the preamplifier outputs and therefore operate with a lower common-mode current, which in turn minimizes the crowbar current …