Scalability

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A Bidirectional Neuromodulation Chipset With Algorithm-Aware AFE Optimization and High-Voltage-Compliant Stimulation

A Bidirectional Neuromodulation Chipset With Algorithm-Aware AFE Optimization and High-Voltage-Compliant Stimulation 150 150
Author(s): Xiaohua Huang, Hoda Yassin, Beatriz Lafuente Alcazar, Arash Akhoundi, Dante G. Muratore

Abstract:

This work presents a bidirectional neuromodulation chipset with 64-channel neural analog front-end (AFE), and a four-channel current stimulator. The chipset employs a heterogeneous architecture, combining a 28-nm low-voltage (LV) CMOS process for the AFE and the digital backend (DBE) to improve area and power efficiency, with a 180-nm high-voltage (HV) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3650066
Publisher: IEEE

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A 298–334-GHz Scalable Injection-Locked Phased-Array Radiator With Second-Subharmonic-Termination-Assisted Waveform Formulation for Power Enhancement

A 298–334-GHz Scalable Injection-Locked Phased-Array Radiator With Second-Subharmonic-Termination-Assisted Waveform Formulation for Power Enhancement 150 150
Author(s): Meng Yang, Liang Wu

Abstract:

This article introduces an injection-locked $4\times 2$ phased-array radiator featuring scalability in both horizontal and vertical dimensions. The system architecture is constructed by sequentially cascading four identical phase-shifting and frequency-quadrupling (PSFQ) elements in a chain-like configuration and then cohering two such chains, thereby achieving global frequency synchronization. Particularly, phase shifting and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3624563
Publisher: IEEE

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A 14-b Energy-Efficient BW/Power Scalable CTDSM With a Frequency-Controlled Current Source

A 14-b Energy-Efficient BW/Power Scalable CTDSM With a Frequency-Controlled Current Source 150 150
Author(s): Xinjie Wu, Xiaopeng Yu, Nick Nianxiong Tan, Zhong Tang

Abstract:

This work presents a 14-bit energy-efficient bandwidth (BW)/power scalable continuous-time delta–sigma modulator (CTDSM) for sensor interfaces in IoT applications. To ensure low noise for small input signals and achieve BW/power scalability, it is built around Gm-C integrators biased via a linear frequency-controlled current source (FCCS). The FCCS …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3621527
Publisher: IEEE

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Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs

Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs 150 150
Author(s): Sadik Yasir Tauki, Rudra Biswas, Rakesh Acharya, Jiahui Duan, Rajiv Joshi, Kai Ni, Vijaykrishnan Narayanan

Abstract:

Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 148 – 156
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3619908
Publisher: IEEE

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A Scalable 1024-Channel Ultra-Low-Power Spike Sorting Chip With Event-Driven Detection and Spatial Clustering

A Scalable 1024-Channel Ultra-Low-Power Spike Sorting Chip With Event-Driven Detection and Spatial Clustering 150 150
Author(s): Arash Akhoundi, Pumiao Yan, Yawende Landbrug, Madeline Hays, Boris Murmann, E. J. Chichilnisky, Dante G. Muratore

Abstract:

This article presents a 1024-channel ultra-low-power spike sorting chip featuring event-driven spike detection and spatial clustering for large-scale neural recording. To address power and scalability constraints in brain–computer interfaces (BCIs), the design integrates a compressive analog-to-digital converter (ADC) with a two-stage spike detector that significantly reduces memory and processing …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3611139
Publisher: IEEE

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