ring oscillator (RO)

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A 94-fs Jitter and −249.3-dB FoM MDLL With Background Calibration of Injection Phase and Slew-Rate Mismatch

A 94-fs Jitter and −249.3-dB FoM MDLL With Background Calibration of Injection Phase and Slew-Rate Mismatch 150 150
Author(s): Dongjun Park, Jae-Yoon Sim, Seon-Kyoo Lee

Abstract:

This article presents a ring oscillator (RO)-based multiplying delay-locked loop (MDLL) that incorporates a dual-background calibration scheme to compensate for both injection phase and slew-rate mismatches. The MDLL employs the proposed frequency/slew-rate detector (FSD) to distinguish both mismatch types by comparing the pulse widths of consecutive output clock …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3648361
Publisher: IEEE

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BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoMREF of −247.9 dB at 3 GHz With a Ring Oscillator

BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoMREF of −247.9 dB at 3 GHz With a Ring Oscillator 150 150
Author(s): Tong Zhang, Yiwen Zhang, Xueke Cai, Weihao Jie, Yanling Zheng, Deyong Li, Yang Zhao, Yongfu Li, Honglan Jiang, Patrick P. Mercier, Hui Wang

Abstract:

This work presents a bandwidth augmented sub-sampling phase-locked loop (BASS-PLL) architecture that features simultaneous out-of-band noise suppression by direct and multipath sampling of the ring oscillator’s (ROs) output and in-band noise suppression via an intrinsic sub-sampling mechanism, ultimately combining the benefits of over-sampling PLLs (OS-PLLs) and sub-sampling PLLs (SS-PLLs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3640726
Publisher: IEEE

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