Resistance

A 180-nm Voltage-Controlled Magneto-Electric RAM With Sub-1-ns Switching Time

A 180-nm Voltage-Controlled Magneto-Electric RAM With Sub-1-ns Switching Time 150 150

Abstract:

Memory performance has emerged as a critical factor influencing both system speed and energy efficiency. However, conventional memory technologies such as embedded Flash (eFlash) and static RAM (SRAM) encounter significant scalability limitations beyond the 28-nm CMOS node. Among novel emerging memory technologies, spin-transfer-torque magnetic RAM (STT-MRAM) has gained prominence due …

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Reference-Load Sharing Scheme: An Area- and Energy-Efficient Nonvolatile Register Design Using MTJ Devices

Reference-Load Sharing Scheme: An Area- and Energy-Efficient Nonvolatile Register Design Using MTJ Devices 150 150

Abstract:

This article proposes a circuit configuration for an area- and energy-efficient nonvolatile register using magnetic tunnel junction (MTJ) devices, suitable for persistent computation in intermittent computing environments. The proposed configuration, named the reference-load sharing scheme (RLSS), stores 1 bit of information using the resistance of a dedicated MTJ device and a …

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A Passive and Scalable High-Order Neuromorphic Circuit Enabled by Mott Memristors

A Passive and Scalable High-Order Neuromorphic Circuit Enabled by Mott Memristors 150 150

Abstract:

In this study, VO2 Mott memristors have been successfully fabricated, leading to the proposal of a passive and scalable high-order neural circuit. This circuit consists of two coupled VO2 Mott memristors, two resistors, and three capacitors. The proposed high-order neural circuit demonstrates 11 distinct firing behaviors similar to those of biological …

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A Low-Power Blocker-Tolerant Wideband Receiver With Bias-Tunable Mixer and Effective Switch Resistance Compensation

A Low-Power Blocker-Tolerant Wideband Receiver With Bias-Tunable Mixer and Effective Switch Resistance Compensation 150 150

Abstract:

This article presents a mixer-first blocker-tolerant receiver (RX) with effective switch resistance ( ${R} _{\text {SW}}$ ) compensation and high-Q selectivity. By analyzing the impact of non-ideal 1/N LO duty cycle and effective ${R} _{\text {SW}}$ on mixer-first RX, an effective ${R} _{\text {SW}}$ compensation technique is proposed to mitigate noise figure (…

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A Multi-Core Series-Resonance CMOS Oscillator

A Multi-Core Series-Resonance CMOS Oscillator 150 150

Abstract:

Multi-core and series-resonance (SR) techniques have been proposed to achieve ultra-low phase noise (PN) performance. In this article, a scalable ring-coupling scheme is proposed for multi-core expansion. The mechanism provides intrinsic oscillation and PN reduction without compromising the passive network, specifically tailored for the SR oscillator. The dual closed ring …

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