Resistance

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A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications

A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications 150 150
Author(s): Maysara Hamada, Mostafa Toubar, Zixu Wang, Nishant Bakshi, Hsiang-Chun Cheng, Mayank Palaria, Joshua Yang, Mike Shuo-Wei Chen

Abstract:

As crossbar-based analog computing grows in popularity for high-speed, energy-efficient processing, the need to drive discrete-time signals to heavy loads arises. This letter presents a novel bi-slewing CMOS driver utilizing high slew-rate error amplifiers and a push–pull stage. The proposed driver achieves a measured settling time of 8.5 ns and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 218 – 221
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3717852
Publisher: IEEE

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Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS

Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS 150 150
Author(s): Jaeyong Jang, Mingu Han, Jaehwan Kim, Taehui Na

Abstract:

This article proposes an offset-canceling (OC) discharge-based sensing circuit (OCDC) for spin-transfer-torque magnetic random access memory (STT-MRAM). The proposed circuit simultaneously implements a merged reference line (MRL) architecture and threshold voltage ( $\mathbf {V}_{\mathbf {TH}}$ ) mismatch cancellation, resolving the structural incompatibility between the conventional OC schemes and MRL. A diode-connection-based, …

Published in: IEEE Solid-State Circuits Letters
Page(s): 210 – 213
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3715234
Publisher: IEEE

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A Compact XOR Gate Implemented With a Single Straintronic Magnetic Tunnel Junction

A Compact XOR Gate Implemented With a Single Straintronic Magnetic Tunnel Junction 150 150
Author(s): Supriyo Bandyopadhyay

Abstract:

The xor Boolean logic gate is widely used in many applications such as encryption (xor ciphers), binary addition (half- and full-adders), error detection (parity bits), etc., but is challenging to construct because of its demanding conditional dynamics. It typically requires multiple logic switches or other types of gates, which results …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 185 – 191
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3719208
Publisher: IEEE

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A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS

A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS 150 150
Author(s): Kshitiz Tyagi, Kunbo Ma, Joung Won Park, Behzad Razavi

Abstract:

We present a transceiver architecture for single-ended PAM4 signaling, introducing an inverter-based active-inductor terminated front-end that obviates the need for further equalizer stages, substantially reducing power and area. Realized in 28-nm CMOS technology, the 4-lane link operates at 64 Gb/s/pin with a bit error rate less than 10-12 while …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3721808
Publisher: IEEE

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A 3-nm FinFET 563-kbit 35.5-Mbit/mm2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode

A 3-nm FinFET 563-kbit 35.5-Mbit/mm2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode 150 150
Author(s): Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Kazuto Mizutani, Masaya Hamada, Yuichiro Ishii, Yen Chi Chou, Jun Cheng Liu, Chien-Yu Huang, Kang-Hui Peng, Yu-Hao Hsu, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Abstract:

This article presents a high-density (HD) 6T SRAM macro designed in 3-nm FinFET technology with an extended dual-rail (XDR) architecture, addressing active energy and leakage for mobile applications. Two key innovations are introduced: the delayed-wordline in write operation (DEWL) technique and a one-cycle latency low-leakage access mode (1-CLM). The XDR …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1466 – 1476
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3639747
Publisher: IEEE

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An 18.4-Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using Four-Phase Hybrid Timing Alignment and Dual Equalization

An 18.4-Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using Four-Phase Hybrid Timing Alignment and Dual Equalization 150 150
Author(s): Minchang Kim, Hankyu Chi, Sooncheol Kwon, Icsu Oh, Seulgi Kim, Heewoong Song, Daeho Yun, Jaehong Jeong, Daejoon Kim, Kichul Hong, Jeonghyun Park, Woo-Seok Choi, Hae-Kang Jung, Hoyoung Son, Inchul Jeong, Hyungsoo Kim, Jonghwan Kim

Abstract:

This letter presents a simultaneous bidirectional (SBD) transceiver for post HBM4. It is difficult to increase the data rate due to poor channel characteristics of the silicon interposer and the limited physical area of the IO in high-bandwidth memory (HBM) interface. SBD signaling is attractive because it doubles the per-pin …

Published in: IEEE Solid-State Circuits Letters
Page(s): 182 – 185
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3696268
Publisher: IEEE

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Minimizing the Noise in Low-Current Sensing by MOSFET p-n Junction Diode Feedback

Minimizing the Noise in Low-Current Sensing by MOSFET p-n Junction Diode Feedback 150 150
Author(s): Ehsan Semsar Parapari, Marco Bennati, Michele Biondi, Marco Crescentini, Federico Thei

Abstract:

This letter proposes a transimpedance amplifier (TIA) architecture that minimizes noise for continuous-time (CT) low-current sensing. The approach leverages a MOSFET to realize a pure p-n junction diode as the TIA feedback element, such that MOS channel conduction is completely suppressed. Therefore, channel-induced noise contributions associated with conventional MOS-based feedback …

Published in: IEEE Solid-State Circuits Letters
Page(s): 162 – 165
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3692971
Publisher: IEEE

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A 1.1-nJ/Conversion RC-Discharge-Based Resistance Sensor With ±0.65% (3σ) 1 -Point Trimmed Inaccuracy in 0.18-μm CMOS Technology

A 1.1-nJ/Conversion RC-Discharge-Based Resistance Sensor With ±0.65% (3σ) 1 -Point Trimmed Inaccuracy in 0.18-μm CMOS Technology 150 150
Author(s): Mu Wu, Yihang Cheng, Xingli Cui, Sining Pan, Huaqiang Wu

Abstract:

This letter presents an energy-efficient RC discharge-based sensor readout circuit for sub-kilo-ohm resistance measurements. An SAR logic is implemented to adjust the DAC capacitor array to equalize the RC time constants of the resistance-sensing and DAC branches, thereby eliminating the high static current required to bias the small sensing resistor. …

Published in: IEEE Solid-State Circuits Letters
Page(s): 109 – 112
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3677301
Publisher: IEEE

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Characterization and Modeling of Multilevel Analog ReRAM Synapses in the Sky130 Process

Characterization and Modeling of Multilevel Analog ReRAM Synapses in the Sky130 Process 150 150
Author(s): Irem Didin, Carl Brando, Ching-Yi Lin, Sahil Shah

Abstract:

Nonvolatile memory devices play a key role in enabling energy-efficient computing. Among them, analog nonvolatile memories such as resistive random access memory (ReRAM) offer high density and low power compared to conventional digital memories. However, their analog nature introduces device-level variability that impacts computational accuracy. This work presents the characterization …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 27 – 35
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3670667
Publisher: IEEE

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