Resistance

A Low-Power, Compact, 0.1–5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR

A Low-Power, Compact, 0.1–5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR 150 150

Abstract:

This article presents a low-power (LP), compact, wideband (WB) low-noise transconductance amplifier (LNTA)-first receiver (RX) designed for software-defined radios (SDRs). It comprises the LNTA, frequency divider, mixer, and trans-impedance amplifier (TIA). The LNTA utilizes a common gate (CG)-common source (CS) structure without on-chip inductors and incorporates gm-boosting and …

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A 2.8 $\mu$ s Response Time 95.1% Efficiency Hybrid Boost Converter With RHP Zero Elimination for Fast-Transient Applications

A 2.8 $\mu$ s Response Time 95.1% Efficiency Hybrid Boost Converter With RHP Zero Elimination for Fast-Transient Applications 150 150

Abstract:

This article proposes a hybrid boost converter that eliminates the right-half-plane (RHP) zero. The proposed converter can be designed with a broad bandwidth up to a tenth of the switching frequency, such that the converter can attain fast transient response as a buck converter. Besides, it features a left-half-plane zero …

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A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking 150 150

Abstract:

A 3-nm FinFET single-port (SP) 6T SRAM macro is proposed that utilizes a far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuits can decrease write cycle time by decreasing the pre-charge period and engaging read cycle time by enhancing the trackability of sense enable timing over supply voltage. …

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A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array

A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array 150 150

Abstract:

Analog computing-in-memory (CIM) using emerging resistive nonvolatile memory (NVM) technologies faces challenges, such as static power consumption, current flow-induced IR drop, and the need for multiple power-hungry ADCs. In this letter, we present ferroelectric capacitive array (FCA)-based energy/area-efficient CIM macro used for charge-domain multiply-and-accumulate operations, which addresses the …

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Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories

Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories 150 150

Abstract:

While magnetic random-access memories (MRAMs) are promising because of their nonvolatility, relatively fast speeds, and high endurance, there are major challenges in adopting them for the advanced technology nodes. One of the major challenges in scaling MRAM devices is caused by the ever-increasing resistances of interconnects. In this article, we …

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