Recording

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A 7.5-μW 35-Keyword End-to-End Keyword Spotting System With Random Augmented On-Chip Training

A 7.5-μW 35-Keyword End-to-End Keyword Spotting System With Random Augmented On-Chip Training 150 150
Author(s): Hyuk-Jin Lee, Kyunghoon Pyo, Taekwang Jang, Mingoo Seok, SeongHwan Cho

Abstract:

Fully integrated keyword spotting (KWS) systems designed for low-power operation face two major challenges. First, increasing the number of supported keywords significantly raises system complexity and power consumption. Second, most existing systems are not personalized to individual users, as they are trained on data from native English speakers, leading to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3660634
Publisher: IEEE

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A Bidirectional Neuromodulation Chipset With Algorithm-Aware AFE Optimization and High-Voltage-Compliant Stimulation

A Bidirectional Neuromodulation Chipset With Algorithm-Aware AFE Optimization and High-Voltage-Compliant Stimulation 150 150
Author(s): Xiaohua Huang, Hoda Yassin, Beatriz Lafuente Alcazar, Arash Akhoundi, Dante G. Muratore

Abstract:

This work presents a bidirectional neuromodulation chipset with 64-channel neural analog front-end (AFE), and a four-channel current stimulator. The chipset employs a heterogeneous architecture, combining a 28-nm low-voltage (LV) CMOS process for the AFE and the digital backend (DBE) to improve area and power efficiency, with a 180-nm high-voltage (HV) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3650066
Publisher: IEEE

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A 32-Channel 85.4 dB SNDR Time-Multiplexed Neural Recording Front-End Achieving Within-Conversion Artifact Recovery

A 32-Channel 85.4 dB SNDR Time-Multiplexed Neural Recording Front-End Achieving Within-Conversion Artifact Recovery 150 150
Author(s): Arindam Mandal, Chi-Hsiang Huang, Julian Arenas, Wei-En Lee, Kevin D. Patino-Sosa, Philip Anschutz, Amanda Jacob, Keshav Ramachandra, Samuel Sober, Muhannad S. Bakir, Shaolan Li, Visvesh S. Sathe

Abstract:

This article presents a 32-channel time-multiplexed highly digital neural recording front-end (RFE) that exhibits sub- $8.8~\mu $ s recovery latency from large stimulation artifacts while delivering high-resolution data at the Nyquist rate. The RFE is time-shared across 32 channels for low-frequency electrocorticography (ECoG) recording and across four channels for high-frequency action potentials (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1053 – 1067
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3643367
Publisher: IEEE

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A 4.6 μW, 133-VPP Common-Mode Interference-Tolerant Biopotential Amplifier for Two-Electrode Recording System in 110-nm CMOS

A 4.6 μW, 133-VPP Common-Mode Interference-Tolerant Biopotential Amplifier for Two-Electrode Recording System in 110-nm CMOS 150 150
Author(s): Yongjae Park, Yeong-Jin Mo, Jeong-Hoon Kim, Gert Cauwenberghs, Seong-Jin Kim

Abstract:

This article presents a biopotential recording analog front-end (AFE) specifically tailored for a two-electrode measurement system, capable of capturing small biopotential signals while tolerating a large common-mode interference (CMI) over 130 VPP. By leveraging the Miller effect, the proposed CMI-Follower provides a significantly low common-mode input impedance ( $Z_{\text {IN-CM-C}}$ ), achieving …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3613410
Publisher: IEEE

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A Scalable 1024-Channel Ultra-Low-Power Spike Sorting Chip With Event-Driven Detection and Spatial Clustering

A Scalable 1024-Channel Ultra-Low-Power Spike Sorting Chip With Event-Driven Detection and Spatial Clustering 150 150
Author(s): Arash Akhoundi, Pumiao Yan, Yawende Landbrug, Madeline Hays, Boris Murmann, E. J. Chichilnisky, Dante G. Muratore

Abstract:

This article presents a 1024-channel ultra-low-power spike sorting chip featuring event-driven spike detection and spatial clustering for large-scale neural recording. To address power and scalability constraints in brain–computer interfaces (BCIs), the design integrates a compressive analog-to-digital converter (ADC) with a two-stage spike detector that significantly reduces memory and processing …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3611139
Publisher: IEEE

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