Quantization (signal)

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DPIM: A 2T1C eDRAM Transformer-in-Memory Chip With Sparsity-Aware Quantization and Heterogeneous Dense–Sparse Core

DPIM: A 2T1C eDRAM Transformer-in-Memory Chip With Sparsity-Aware Quantization and Heterogeneous Dense–Sparse Core 150 150
Author(s): Donghyuk Kim, Jae-Young Kim, Hyunjun Cho, Seungjae Yoo, Sukjin Lee, Sungwoong Yune, Sejeong Yang, Hoichang Jeong, Keonhee Park, Ki-Soo Lee, Jongchan Lee, Chanheum Han, Gunmo Koo, Yuli Han, Jaejin Kim, Jaemin Kim, Kyuho Jason Lee, Joo-Hyung Chae, Kunhee Cho, Joo-Young Kim

Abstract:

Transformer models have revolutionized artificial intelligence (AI) applications across various domains, but their increasing complexity poses significant challenges in terms of computational and memory demands. While processing-in-memory (PIM) paradigms have been adopted to address these limitations, existing PIM-based transformer accelerators still face hurdles such as: 1) focusing solely on optimizing attention …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3607826
Publisher: IEEE

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A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique

A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique 150 150
Author(s): Sungjin Kim, Jeonghyun Lee, Yoonse Cho, Jintae Kim, Jaehyouk Choi, Heein Yoon

Abstract:

This letter presents a 7-bit pipelined subranging ADC that integrates a 3-bit flash ADC with a ring VCO-based quantizer. A resistor-ladder-based residue shifter (RLRS) replaces traditional residue amplifiers, efficiently shifting the residue voltage into the most linear region of the $K_{textrm {VCO}}$ , thereby eliminating the need for post-linearity calibration. …

Published in: IEEE Solid-State Circuits Letters
Page(s): 177 – 180
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3578546
Publisher: IEEE

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