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Design and Analysis of a 13.7–41 GHz Ultra-Wideband Frequency Doubler With Cross-Coupled Push-Push Structure

Design and Analysis of a 13.7–41 GHz Ultra-Wideband Frequency Doubler With Cross-Coupled Push-Push Structure 150 150
Author(s): Kai Li, Keping Wang, Fanyi Meng, Kiat Seng Yeo, Kaixue Ma

Abstract:

This article presents a 13.7–41 GHz ultra-wideband frequency doubler with high efficiency and conversion gain (CG). The proposed cross-coupled push-push structure, in conjunction with the fourth-order transformer-based resonator and the series gate inductor, collaboratively shapes the input signal amplitude such that three distinct peaks emerge at different frequencies, thereby significantly improving …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3667289
Publisher: IEEE

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A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS

A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS 150 150
Author(s): Shankkar Balasubramanian, Kristof Vaesen, Piet Wambacq, Carsten Wulff

Abstract:

This letter presents a frequency quadrupler with 32% fractional bandwidth (66–92 GHz) and 5% peak power-added efficiency (PAE), capable of operating with an input power of 0 dBm. The quadrupler consisting of two cascaded frequency doublers uses a multiport driven push-push complementary architecture for the first stage to generate differential signals for the second …

Published in: IEEE Solid-State Circuits Letters
Page(s): 301 – 304
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3614381
Publisher: IEEE

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