Programming

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A Runtime Reconfigurable Array (RTRA) for Multiprogram ML and DSP Acceleration With Hierarchical Partitioning and On-Chip Multilevel Scheduling

A Runtime Reconfigurable Array (RTRA) for Multiprogram ML and DSP Acceleration With Hierarchical Partitioning and On-Chip Multilevel Scheduling 150 150
Author(s): Hongseok Lee, Jack Burd, Tim Ling, Yao-Kai Yang, Nian-Shyang Chang, Wen-Ching Chen, Chi-Shi Chen, Tzi-Dar Chiueh, Michael Kuan-Tse Lee, Chia-Hsiang Yang, Dejan Marković

Abstract:

Emerging applications with highly dynamic digital signal processing (DSP) and machine-learning (ML) workloads demand a hardware platforms that simultaneously deliver high performance, high energy efficiency, and low-latency reconfiguration. Such systems must adapt to evolving algorithms, variable data rates, and multiprogram tenancy without incurring prohibitive switching overhead. The conventional reconfigurable architectures …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5296 – 5312
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715500
Publisher: IEEE

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A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI

A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI 150 150
Author(s): Jiho Chun, Byeongseon Choi, Edward Jongyoon Choi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je

Abstract:

Computing in memory (CIM) has emerged as a promising architecture that can significantly reduce power consumption and latency in edge artificial intelligence (AI) devices. For battery-constrained edge devices, non-volatile memories (NVMs) are ideal due to their ability to retain neural network parameters even when powered down, ensuring rapid response time …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3717139
Publisher: IEEE

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Leveraging a Passive MRAM Crossbar for Hardware-in-the-Loop and Continual learning

Leveraging a Passive MRAM Crossbar for Hardware-in-the-Loop and Continual learning 150 150
Author(s): M. Drouhin, M. Grelier, M. Deroo, Y. Sassi, E. Monteblanco, N. Davila, G. Mihajlović, R. V. Chopdekar, T. S. Santos, J. A. Katine, D. Ravelosona

Abstract:

Artificial neural networks (ANNs) have enabled major advances in artificial intelligence, yet their growing computational and energy demands challenge conventional von Neumann architectures due to the costly separation of memory and processing. In-memory computing has emerged as a promising solution, particularly through memristive crossbar arrays capable of performing multiply-and-accumulate operations …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 129 – 134
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3702001
Publisher: IEEE

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Characterization and Modeling of Multilevel Analog ReRAM Synapses in the Sky130 Process

Characterization and Modeling of Multilevel Analog ReRAM Synapses in the Sky130 Process 150 150
Author(s): Irem Didin, Carl Brando, Ching-Yi Lin, Sahil Shah

Abstract:

Nonvolatile memory devices play a key role in enabling energy-efficient computing. Among them, analog nonvolatile memories such as resistive random access memory (ReRAM) offer high density and low power compared to conventional digital memories. However, their analog nature introduces device-level variability that impacts computational accuracy. This work presents the characterization …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 27 – 35
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3670667
Publisher: IEEE

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On-Chip Charge-Trap-Transistor-Based Mismatch Calibration of an 8-Bit Thermometer Current-Source DAC

On-Chip Charge-Trap-Transistor-Based Mismatch Calibration of an 8-Bit Thermometer Current-Source DAC 150 150
Author(s): Mohammadreza Zeinali, Sudhakar Pamarti

Abstract:

This letter presents an on-chip mismatch calibration technique for current-source digital-to-analog converters (DACs) using charge-trap transistors (CTTs) in 22-nm FDSOI technology. The proposed method exploits programmable threshold voltage (VTH) shifts in CTTs to locally tune the current of near-minimum-sized devices without external trimming. A compact 8-bit thermometer DAC is implemented …

Published in: IEEE Solid-State Circuits Letters
Page(s): 53 – 56
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3656261
Publisher: IEEE

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A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC

A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC 150 150
Author(s): Vaidehi Garg, Jianwei Jia, Omkar Phadke, Shimeng Yu

Abstract:

Compute-in-memory (CIM) using emerging nonvolatile memory devices is a promising candidate for energy-efficient deep neural network (DNN) inference at the edge. Ferroelectric field-effect transistors (FeFETs) have recently gained attention as nonvolatile, CMOS-compatible devices with a higher on/off ratio and lower read and write energy compared to resistive random-access memory (…

Published in: IEEE Solid-State Circuits Letters
Page(s): 13 – 16
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3640522
Publisher: IEEE

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