process variation

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A 42-Gb/s PAM-3 Transmitter With a CML Driver and a Dual-Mode Encoder for Process-Variation-Tolerant Middle-Level Generation

A 42-Gb/s PAM-3 Transmitter With a CML Driver and a Dual-Mode Encoder for Process-Variation-Tolerant Middle-Level Generation 150 150
Author(s): Seungwoo Park, Taehwan Kim, Changmin Sim, Seongcheol Kim, Junseob So, Hwaseok Shin, Seon-Been Lee, Chulwoo Kim

Abstract:

This letter presents a 42-Gb/s differential pulse-amplitude modulation (PAM-3) transmitter using a current-mode logic (CML) driver and a dual-mode 3B2T encoder for process-variation-tolerant middle-level (M-level) generation. The encoder selects between two M-level encoding schemes to compensate for load-resistor and driver-current-path mismatches with minimal logic overhead, reducing the standard …

Published in: IEEE Solid-State Circuits Letters
Page(s): 234 – 237
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3720204
Publisher: IEEE

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CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability

CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability 150 150
Author(s): Sufia Shahin, Swati Deshwal, Anirban Kar, Mahdi Benkhelifa, Yogesh S. Chauhan, Hussam Amrouch

Abstract:

This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging effects. A rigorously calibrated TCAD model, validated against experimental CFET data, is employed to quantify the impact of metal gate granularity (MGG)-induced …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 51 – 59
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3568622
Publisher: IEEE

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