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Algorithm–Architecture Co-Design for Vertically Integrated AI and HPC Systems: Challenges, Advantages, and Future Outlook

Algorithm–Architecture Co-Design for Vertically Integrated AI and HPC Systems: Challenges, Advantages, and Future Outlook 150 150
Author(s): Patricia Gonzalez-Guerrero, Aaron R. Young, Giuseppe Di Guglielmo, Benjamin Parpillon, Narasinga Rao Miniskar, Nikhil Kumar Cherukuri, Abhay Nayak, Meriam Gay Bautista-Jurney, Mario Vega, George Michelogiannakis, Thom Popovici, Yu Cao, Jeffrey S. Vetter, John Shalf, Farah Fahim

Abstract:

Next-generation scientific instruments in high-energy physics, X-ray imaging, fusion diagnostics, and other data-intensive applications generate data rates that increasingly exceed practical communication bandwidth and power budgets, making the traditional approach of transferring raw data to remote computing systems unsustainable. This paper presents the Vertically Integrated AI for Sensing and High-Performance …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3742652
Publisher: IEEE

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An Intelligent Vision SoC With Fully Analog Sensing-to-Inference Pipeline and Linearity-Recovery RRAM Compute-in-Memory

An Intelligent Vision SoC With Fully Analog Sensing-to-Inference Pipeline and Linearity-Recovery RRAM Compute-in-Memory 150 150
Author(s): Zhengke Yang, Xiao Liu, Haofeng Yu, Zhen Kong, Humiao Li, Liang Ran, Zhichao Lu, Xinhe Feng, Liang Zhao, Yida Li, Jiamin Li, Feichi Zhou, Longyang Lin

Abstract:

Edge vision systems that integrate image sensing and neural-network inference on a single chip are constrained by inter-layer analog-to-digital converters (ADCs) and on-chip weight storage density, which together limit system efficiency and network scale. This article presents a fully analog vision system-on-chip (SoC) with 2-Mbit multi-level-cell (MLC) resistive random access …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3737258
Publisher: IEEE

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A Modeling/Rendering Unified 3DGS Processor Based on Locality-Optimized Computation and Reconfigurable Architecture

A Modeling/Rendering Unified 3DGS Processor Based on Locality-Optimized Computation and Reconfigurable Architecture 150 150
Author(s): Xiaoyu Feng, Hedi Wang, Songran Xiao, Huazhong Yang, Yongpan Liu

Abstract:

Traditional 3-D Gaussian-splatting (3DGS) modeling relies on iterative optimization, leading to substantial latency and limited generalizability. Feedforward 3DGS alleviates these limitations by generating Gaussians through a single network inference. However, most existing processors are optimized for optimization-based 3DGS and do not fully exploit the distinct computational characteristics of feedforward 3DGS. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3737807
Publisher: IEEE

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A 28-nm CMOS 1-Chip In-Pixel Memory Backplane Circuit for 1800 × 1350 6652-PPI MicroLED AR Glasses With Per-Pixel Current Sensing and Compensation

A 28-nm CMOS 1-Chip In-Pixel Memory Backplane Circuit for 1800 × 1350 6652-PPI MicroLED AR Glasses With Per-Pixel Current Sensing and Compensation 150 150
Author(s): Sunkwon Kim, Yongil Kwon, Youngkil Choi, Taehyun Kwon, Seongyoung Ryu, Sewhan Na, Kangjoo Kim, Uijong Song, Heejin Lee, Hyun-Wook Lim, Jongwoo Lee, Jae-Youl Lee

Abstract:

This article presents a 28-nm CMOS 1-chip LED-on-Silicon (LEDoS) backplane (BP) for 6652-pixel-per-inch (PPI) microLED ( $mu $ LED) augmented reality (AR) displays. To address power and display quality challenges in AR glasses, the proposed BP employs two low-power techniques: self-refresh and partial update, and introduces four display quality enhancement methods: MSB …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3737236
Publisher: IEEE

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Raisu: A Radiation-Tolerant Neuromorphic Imager With In-Pixel Self-Healing and Unified Spiking Processing for Spaceborne Vision

Raisu: A Radiation-Tolerant Neuromorphic Imager With In-Pixel Self-Healing and Unified Spiking Processing for Spaceborne Vision 150 150
Author(s): Quan Cheng, Qiufeng Li, Zhengke Yang, Zhen Kong, Gaoqiang Niu, Yuan Liang, Jiamin Li, Jeong Hoan Park, Wang Liao, Hiromitsu Awano, Takashi Sato, Longyang Lin, Masanori Hashimoto

Abstract:

Spaceborne imaging systems operate under severe radiation and energy constraints, where single-event effects (SEEs), total ionizing dose (TID), and displacement damage dose (DDD) critically degrade reliability and performance. This work presents a radiation-tolerant neuromorphic imager prototype featuring a fully spike-based neuromorphic vision architecture with in-pixel self-healing capability and an integrated …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715724
Publisher: IEEE

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TD-dAJC: A 100 MS/s 2 pJ/Pixel Time-Domain Weight and Integrating-MAC-Based Direct Analog to MJPEG Compression for Video Sensor Nodes

TD-dAJC: A 100 MS/s 2 pJ/Pixel Time-Domain Weight and Integrating-MAC-Based Direct Analog to MJPEG Compression for Video Sensor Nodes 150 150
Author(s): Harshit Naman, Gourab Barik, Yudhajit Ray, Shreyas Sen

Abstract:

Always-on, high-quality video sensors are increasingly required in wearables, surveillance, and Internet-of-Things (IoT) devices, where stringent energy constraints make efficient in-sensor compression necessary. These systems must support high-definition (HD) and 4 K video, yet conventional digital video compression pipelines consume significant power because high-speed analog-to-digital converters (ADCs) must digitize every pixel, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3712196
Publisher: IEEE

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A 96 × 64 SPAD LiDAR Sensor With 6× Imaging FoM Promotion by AI-Assisted Fusion of 2-D and Edge-Guided Sparse 3-D Detection

A 96 × 64 SPAD LiDAR Sensor With 6× Imaging FoM Promotion by AI-Assisted Fusion of 2-D and Edge-Guided Sparse 3-D Detection 150 150
Author(s): Bu Chen, Qi Zheng, Zikun Cai, Hankun Lv, Jingyi Wang, Jun Han, Zhangcheng Huang, Jianlu Wang, Qi Liu, Ming Liu

Abstract:

Flash-mode direct time-of-flight (dToF) light detection and ranging (LiDAR) is widely adopted in autonomous systems and robotics due to its capability for accurate depth measurement and robustness under challenging lighting conditions. However, scaling single-photon avalanche diode (SPAD)-based dToF pixel arrays toward higher resolution 3-D imaging introduces significant challenges in …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3714508
Publisher: IEEE

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QVGA CMOS LiDAR Sensor With nMOS-Only SPAD Analog Front-End and Area-Efficient Priority Histogramming TDC

QVGA CMOS LiDAR Sensor With nMOS-Only SPAD Analog Front-End and Area-Efficient Priority Histogramming TDC 150 150
Author(s): Minkyung Kim, Hyeongseok Seo, Songhyeon Kim, Jung-Hoon Chun, Seong-Jin Kim, Jaehyuk Choi

Abstract:

This article presents a high-resolution (HR) CMOS light detection and ranging (LiDAR) sensor capable of generating quarter video graphics array (QVGA) ( $320~{\times }~240$ ) depth images. To support high pixel density, the sensor employs a compact 6-transistor (6-T) nMOS-only single-photon avalanche diode (SPAD) analog front-end (AFE) with a column-shared active recharge circuit. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3687569
Publisher: IEEE

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