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A 27.5–28.5 mJ/Frame 3-D Gaussian Rendering Processor With Spherical Beta Illumination and Mixed-Precision Computation Path

A 27.5–28.5 mJ/Frame 3-D Gaussian Rendering Processor With Spherical Beta Illumination and Mixed-Precision Computation Path 150 150
Author(s): Cheng Nian, Xiaorui Mo, Jiaqi Zhang, Fasih Ud Din Farrukh, Jiaying Peng, Fei Chen, Chun Zhang

Abstract:

This letter presents a 3-D Gaussian rendering processor that integrates a spherical beta (SB) illumination module with a mixed-precision rendering engine to enable energy-efficient novel-view synthesis on edge devices. SB replaces spherical harmonics (SH) with a hardware-efficient kernel implemented using a pipelined fixed-point piecewise linear (PWL) power unit. The pipeline …

Published in: IEEE Solid-State Circuits Letters
Page(s): 113 – 116
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3676726
Publisher: IEEE

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Birch: A Real-Time Multi-Domain Multi-Task Extended Reality Perception Accelerator

Birch: A Real-Time Multi-Domain Multi-Task Extended Reality Perception Accelerator 150 150
Author(s): Kathleen Feng, Kai Bartolone, Kartik Prabhu, Brianna McColm, Xingyu Ni, Siddhant Gupta, Priyanka Raina

Abstract:

Birch is a system-on-chip (SoC) that efficiently and accurately accelerates the multi-task multi-domain extended reality (XR) perception pipeline, with workloads such as visual inertial odometry (VIO), eye gaze tracking, and scene understanding. Birch features vision modules with cascaded line buffers, in-step feature sorting, and double-buffered optical flow to extract and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 121 – 124
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3673168
Publisher: IEEE

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A 39.4-mW 300 MHz-BW 70.9 dB-SNDR Hybrid ADC With Resistive Input and 200 fs, rms-Jitter Tolerance

A 39.4-mW 300 MHz-BW 70.9 dB-SNDR Hybrid ADC With Resistive Input and 200 fs, rms-Jitter Tolerance 150 150
Author(s): Yanquan Luo, Mingtao Zhan, Yi Zhong, Nan Sun

Abstract:

This letter presents a power-efficient hybrid ADC architecture: a low-resolution continuous-time (CT) delta-sigma modulator (DSM) followed by a time-interleaved pipeline stage which further quantizes the quantization noise of the DSM. In the frontend CT DSM, the resistive input makes the ADC easy-to-drive, and the direct-charge-dump feedback (DCD FB) provides a …

Published in: IEEE Solid-State Circuits Letters
Page(s): 61 – 64
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3656180
Publisher: IEEE

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A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm2-17 TFLOPS/mm2 SRAM-Based INT8, and FP16 Digital-CIM Compiler With Support for Multi-Weight Update/Cycle

A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm2-17 TFLOPS/mm2 SRAM-Based INT8, and FP16 Digital-CIM Compiler With Support for Multi-Weight Update/Cycle 150 150
Author(s): Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Kinshuk Khare, Brian Crafton, Hiroaki Ishii, Cheng-En Lee, Xiaochen Peng, Xiaoyu Sun, Yorinobu Fujino, Chia-Jung Tsen, Vineet Joshi, Chao-Kai Chuang, Takeshi Hashizume, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Hidehiro Fujiwara, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Abstract:

This article presents an static random-access memory (SRAM)-based digital compute-in-memory (CIM) compiler implemented with 3 nm high- $\kappa $ metal gate (HKMG) FinFET technology, supporting flexible INT8 and FP16 formats for weight and activation multiply-accumulate (MAC) operations, offering configuration flexibility, high accuracy, and improved area and power efficiency. The FP16 digital …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3646072
Publisher: IEEE

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Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications

Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications 150 150
Author(s): Po-Han Chen, Bo Wun Cheng, Michael Oduoza, Zhouhua Xie, Rupert Lu, Sai Gautham Ravipati, Kalhan Koul, Alex Carsello, Yuchen Mei, Mark Horowitz, Priyanka Raina

Abstract:

Sparsity has recently attracted increased attention in the machine learning (ML) community due to its potential to improve performance and energy efficiency by eliminating ineffectual computations. As ML models evolve rapidly, reconfigurable architectures, such as coarse-grained reconfigurable arrays (CGRAs), are being explored to adapt to and accelerate emerging models. Previous …

Published in: IEEE Solid-State Circuits Letters
Page(s): 293 – 296
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3613245
Publisher: IEEE

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