phase noise

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A 60-GHz Class- F2,3 Standing-Wave Oscillator Employing Triple-Line Resonator Achieving −189-dBc/Hz FoM in 65-nm CMOS

A 60-GHz Class- F2,3 Standing-Wave Oscillator Employing Triple-Line Resonator Achieving −189-dBc/Hz FoM in 65-nm CMOS 150 150
Author(s): Wei-Yu Lin, Nikhil Jain, Jun-Chau Chien

Abstract:

Implementing oscillators with harmonic engineering beyond 60-GHz poses significant challenges due to the need for small inductors resonating beyond 120 GHz. To address this issue, this work presents a 60-GHz standing-wave oscillator (SWO) with both second- and third-harmonic boosting for phase noise reduction. A triple-line resonator is proposed to sustain both …

Published in: IEEE Solid-State Circuits Letters
Page(s): 158 – 161
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3693153
Publisher: IEEE

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A 550-μW Capacitor-Assisted Transformer-Based VCO Achieving 204-dBc/Hz FoMA at 1-MHz Frequency Offset

A 550-μW Capacitor-Assisted Transformer-Based VCO Achieving 204-dBc/Hz FoMA at 1-MHz Frequency Offset 150 150
Author(s): Teng-Shen Yang, Liang-Hung Lu

Abstract:

This letter presents a capacitor-assisted transformer (CTF)-based voltage-controlled oscillator (VCO) that achieves a low flicker-noise corner with submilliwatt power consumption and compact chip area. By introducing a small assisting capacitor into the transformer, the higher order tank impedance is reshaped from the second-resonance region toward the third-resonance region, resulting …

Published in: IEEE Solid-State Circuits Letters
Page(s): 150 – 153
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3690818
Publisher: IEEE

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A 6.8–14-GHz Ring-Based Sampling-PLL Achieving 69.3-fs Jitter Under 50-mV Supply Noise

A 6.8–14-GHz Ring-Based Sampling-PLL Achieving 69.3-fs Jitter Under 50-mV Supply Noise 150 150
Author(s): Mahmoud A. Khalil, Mohamed Badr Younis, Ruhao Xia, Ahmed E. Abdelrahman, Tianyu Wang, Kyu-Sang Park, Pavan Kumar Hanumolu

Abstract:

This article presents a type-III wide-bandwidth ring-oscillator-based analog phase-locked loop (PLL) optimized for low-jitter performance in noisy supply environments. The design uses an 812.5-MHz reference frequency and a high-gain sampling phase detector to achieve a closed-loop bandwidth over 100 MHz, effectively reducing the intrinsic phase noise of the ring oscillator. To …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3683111
Publisher: IEEE

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A 16-MHz CMOS RC Frequency Reference Achieving Accuracies of ±125 ppm From −40 °C to 85 °C and −560/+580 ppm After Accelerated Aging

A 16-MHz CMOS RC Frequency Reference Achieving Accuracies of ±125 ppm From −40 °C to 85 °C and −560/+580 ppm After Accelerated Aging 150 150
Author(s): Runtao Huo, Weihao Jie, Yiwen Zhang, Honglan Jiang, Hui Wang

Abstract:

This article presents a low-power, high-accuracy CMOS RC frequency reference featuring a capacitively modulated RC time constant (CMT) generation and a die-to-die error removal (DDER) technique for precise frequency generation with a low-calibration cost. Unlike resistive trimming, the temperature dependence of the on-chip resistor is compensated by a $\Delta \Sigma $ …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3684094
Publisher: IEEE

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A Low-Jitter Fractional-N Sampling PLL With Voltage-Domain Quantization-Error Cancellation Using a Nonlinearity-Replication Technique

A Low-Jitter Fractional-N Sampling PLL With Voltage-Domain Quantization-Error Cancellation Using a Nonlinearity-Replication Technique 150 150
Author(s): Yuhwan Shin, Juyeop Kim, Junseok Lee, Yongwoo Jo, Jaehyouk Choi

Abstract:

This work presents a low-jitter, low-fractional-spur fractional- $N$ digital sampling phase-locked loop (SPLL) that generates output frequencies from 10.4to 11.8GHz. Conventional fractional- $N$ PLLs employ a digital-to-time converter (DTC) to cancel the quantization error (Q-error) of the delta-sigma modulator ( $Delta Sigma $ M). To address the nonlinearity (NL) of the DTC, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3681940
Publisher: IEEE

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A Wideband Digitally Assisted Frequency Tripler With Adaptively Optimized Output Power in 55-nm SiGe BiCMOS

A Wideband Digitally Assisted Frequency Tripler With Adaptively Optimized Output Power in 55-nm SiGe BiCMOS 150 150
Author(s): Daniele Lodi Rizzini, Francesco Tesolin, Michele Rossoni, Riccardo Moleri, Filippo Osio, Andrea Mazzanti, Andrea L. Lacaita, Simone M. Dartizio, Salvatore Levantino

Abstract:

This article presents a 28–38-GHz frequency tripler implemented in 55-nm SiGe BiCMOS technology with a novel on-chip background calibration technique. This technique continuously optimizes the circuit performance by maximizing output power and improving fundamental harmonic rejection. The proposed tripler achieves wideband operation and robust performance across varying operating conditions and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1844 – 1859
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3666591
Publisher: IEEE

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A 23.4–42.1-GHz Fractional-N Synthesizer With ADC-Based Direct Phase Digitization

A 23.4–42.1-GHz Fractional-N Synthesizer With ADC-Based Direct Phase Digitization 150 150
Author(s): Hao Xu, Yizhuo Wang, Ziyang Jiao, Guoyu Li, Yiyun Mao, Shuai Liu, Yan Liu, Jimiao Sang, Qi Guo, Long Kong, Na Yan

Abstract:

A fractional-N digital phase-locked loop employs a novel analog-to-digital converter (ADC)-based phase detector (PD) to achieve direct phase digitization, thereby eliminating the need for a digital-to-time converter (DTC). The high PD gain reduces in-band phase noise, while its high linearity enables all-digital $\Sigma \Delta $ quantization noise cancellation. Implemented with …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3671094
Publisher: IEEE

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A Low-Reference-Spur Injection-Locked Clock Multiplier Using Sub-Sampling Frequency Tracking Loop and Injection Pulse Timing Calibrator

A Low-Reference-Spur Injection-Locked Clock Multiplier Using Sub-Sampling Frequency Tracking Loop and Injection Pulse Timing Calibrator 150 150
Author(s): Hyeonjun Nam, Hyogyoung An, Changmin An, Sungjin Kim, Heein Yoon

Abstract:

This article presents an injection-locked clock multiplier (ILCM) achieving the low-reference spur (spur ${}_{\mathrm {REF}}$ ) with minimal overhead of a calibrator. To remove the dominant sources of frequency error, which are frequency drift ( $f_{\mathrm {DF}}$ ), phase offset ( $\varPhi _{\mathrm {OS}}$ ), and injection-induced phase error ( $\varPhi _{\mathrm {INJ}}$ ), the ILCM …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3650135
Publisher: IEEE

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A 94-fs Jitter and −249.3-dB FoM MDLL With Background Calibration of Injection Phase and Slew-Rate Mismatch

A 94-fs Jitter and −249.3-dB FoM MDLL With Background Calibration of Injection Phase and Slew-Rate Mismatch 150 150
Author(s): Dongjun Park, Jae-Yoon Sim, Seon-Kyoo Lee

Abstract:

This article presents a ring oscillator (RO)-based multiplying delay-locked loop (MDLL) that incorporates a dual-background calibration scheme to compensate for both injection phase and slew-rate mismatches. The MDLL employs the proposed frequency/slew-rate detector (FSD) to distinguish both mismatch types by comparing the pulse widths of consecutive output clock …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3648361
Publisher: IEEE

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