Phase locked loops

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A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse
A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse 150 150
Author(s): Taylor Barton, Shea Smith, Yu Hao, Ryan Watson, Kyle Rogers, Parker Allred, Bibhu Datta Sahoo, Nancy Fulda, Jordan T. Yorgason, Karl F. Warnick, Mau-Chung Frank Chang, Yen-Cheng Kuan, Shiuh-Hua Wood Chiang

Abstract:

The design and measurement of a time-domain analog spiking neuron is described. The proposed neuron leverages time-domain processing using voltage-controlled oscillators (VCOs) and a time-domain comparator to integrate the input spike and trigger the output spike. A novel leaky circuit uses a phase-locked loop (PLL) to drive the phase difference …

Published in: IEEE Solid-State Circuits Letters
Page(s): 143 – 146
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3384762
Publisher: IEEE

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A Radiation-Hardened 15–22-GHz Frequency Synthesizer in 22-nm FinFET
A Radiation-Hardened 15–22-GHz Frequency Synthesizer in 22-nm FinFET 150 150
Author(s): David Dolt, Samuel Palermo

Abstract:

High-speed radiation-hardened frequency synthesizers are a key block in spaceborne communications systems. This article presents a 15–22-GHz radiation-hardened phase-locked loop (PLL) designed in a 22-nm FinFET process with hardening techniques for single-event upset (SEU) and total ionizing dose (TID) implemented in all key PLL blocks. Electrical performance tradeoffs arising from …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3380589
Publisher: IEEE

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A 6.4-Gb/s/pin nand Flash Memory Multichip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems
A 6.4-Gb/s/pin nand Flash Memory Multichip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems 150 150
Author(s): Shinichi Ikeda, Akira Iwata, Goichi Otomo, Tomoaki Suzuki, Hiroaki Iijima, Mikio Shiraishi, Shinya Kawakami, Masatomo Eimitsu, Yoshiki Matsuoka, Kiyohito Sato, Shigehiro Tsuchiya, Yoshinori Shigeta, Takuma Aoyama

Abstract:

This letter describes a NAND flash memory multichip package (NAND MCP) incorporating a developed LSI interface (IF) Chip (Bridge Chip) in which the IF to and from the solid-state drive (SSD) controller has twice the speed as that of the IF to and from the NAND dies even with multiple …

Published in: IEEE Solid-State Circuits Letters
Page(s): 115 – 118
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3377263
Publisher: IEEE

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A 6 to 12-GHz Fractional- $N$ Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays
A 6 to 12-GHz Fractional- $N$ Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays 150 150
Author(s): Aditya Narayanan, Abhishek Bhat, Nagendra Krishnapura

Abstract:

This article presents a frequency synthesizer for generating quadrature local-oscillator (LO) waveforms covering an octave range of 6 to 12-GHz. It uses two voltage-controlled oscillators (VCO) to cover an octave range from 12 to 24 GHz. The VCOs employ inductor mode switching in addition to conventional capacitor switching to obtain a wide tuning …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3373620
Publisher: IEEE

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