Phase locked loops

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A 23.4–42.1-GHz Fractional-N Synthesizer With ADC-Based Direct Phase Digitization

A 23.4–42.1-GHz Fractional-N Synthesizer With ADC-Based Direct Phase Digitization 150 150
Author(s): Hao Xu, Yizhuo Wang, Ziyang Jiao, Guoyu Li, Yiyun Mao, Shuai Liu, Yan Liu, Jimiao Sang, Qi Guo, Long Kong, Na Yan

Abstract:

A fractional-N digital phase-locked loop employs a novel analog-to-digital converter (ADC)-based phase detector (PD) to achieve direct phase digitization, thereby eliminating the need for a digital-to-time converter (DTC). The high PD gain reduces in-band phase noise, while its high linearity enables all-digital $\Sigma \Delta $ quantization noise cancellation. Implemented with …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3671094
Publisher: IEEE

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A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique

A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique 150 150
Author(s): Riccardo Moleri, Simone M. Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Abstract:

This work presents a digital-to-time converter (DTC)-based fractional-N digital phase-locked loop (PLL) designed to achieve simultaneously low jitter and low spurs. We introduce a novel DTC chopping technique that effectively mitigates fractional spurs, which we identify as predominantly arising from even-order nonlinearity invariable-slope (VS) DTCs. The proposed technique suppresses …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663074
Publisher: IEEE

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A 60-GHz Low-Noise mmWave Divider-Less Fractional-N Cascaded PLL Achieving −250.2-dB FoMJ in 28-nm CMOS

A 60-GHz Low-Noise mmWave Divider-Less Fractional-N Cascaded PLL Achieving −250.2-dB FoMJ in 28-nm CMOS 150 150
Author(s): Jaehong Jung, Eunseok Lee, Donghyeon Han, Jinchen Wang, Anantha P. Chandrakasan, Ruonan Han

Abstract:

This article presents a fractional- ${ {N}}$ cascaded phase-locked loop (PLL) operating in the mmWave band from 55.8 to 64.2 GHz. The cascaded architecture consists of a first-stage fractional- ${ {N}}$ reference-sampling (RS) PLL and a second-stage sub-sampling (SS) PLL, incorporating two key innovations. The first-stage RS-PLL leverages a fully differential voltage-domain quantization-noise cancellation (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3652928
Publisher: IEEE

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A 0.29 pJ/b 5.27 Tb/s/mm UCIe Advanced Package Link With 2.5-D CoWoS Interposer and a 0.52 pJ/b 0.448 Tb/s/mm UCIe Standard Package Link With Organic Substrate in 3 nm FinFET

A 0.29 pJ/b 5.27 Tb/s/mm UCIe Advanced Package Link With 2.5-D CoWoS Interposer and a 0.52 pJ/b 0.448 Tb/s/mm UCIe Standard Package Link With Organic Substrate in 3 nm FinFET 150 150
Author(s): Didem Turker Melek, James Vandersand, R. Navin Kumar, Pyare M. Sarkar, Prakash BS, Adrian Leuciuc, Kevin Geary, Shaojun Ma, Chirag M. Mehta, Basant Bothra, Shashi Jain, Pawan Sabharwal, Ranjan Vaish, Kirti Bhanushali, Yutong Ding, Craig Frost, John Annunziata, Krishanu Sadhu, Dimitris Kyritsis, Jeff Bostak, Ming Li, Steve Williams, Ken Chang

Abstract:

This work presents two die-to-die (D2D) wireline transceivers, one compliant with the UCIe advanced package (UCIe-AP) and the other with the UCIe standard package (UCIe-SP) standard, developed in 3 nm FinFET. The Universal Chiplet interconnect express (UCIe)-AP link has 64 RX and 64 TX data lanes in one PHY module and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3651425
Publisher: IEEE

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A 77-fJ/bit 8-Gbps Adaptive-Voltage-Compatible Self-Timed Die-to-Die Link for 2.5-D and 3-D Interconnect in 3 nm

A 77-fJ/bit 8-Gbps Adaptive-Voltage-Compatible Self-Timed Die-to-Die Link for 2.5-D and 3-D Interconnect in 3 nm 150 150
Author(s): Brian Zimmer, Stephen G. Tell, C. Thomas Gray

Abstract:

This work presents a self-timed die-to-die link that serializes four data bits per pin for 2.5-D, or 3-D interconnects using a standard adaptive digital clock and voltage supply. The link achieves 8 Gbps of per-pin bandwidth with a latency of one cycle, energy efficiency of 77 fJ/b, and bandwidth density of 44…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3658215
Publisher: IEEE

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A 19.4-fsRMS Jitter 0.1-to-44-GHz Cryo-CMOS Fractional-N CP-PLL Featuring Automatic Bleed Calibration for Quantum Computing

A 19.4-fsRMS Jitter 0.1-to-44-GHz Cryo-CMOS Fractional-N CP-PLL Featuring Automatic Bleed Calibration for Quantum Computing 150 150
Author(s): Jinhai Xiao, Yong Chen, Ningyi Zhang, Xiaolong Liu, Rui Liu, Junao Zhu, Chenghao Zhang, Peng Luo, Maliang Liu, Yintang Yang, Xiaohua Ma, Yue Hao

Abstract:

Cryogenic fractional- $N$ phase-locked loops (PLLs) are essential for large-scale superconducting quantum computing, and serve as integrated pump sources for Josephson parametric amplifiers. These PLLs enable high-fidelity qubit readout while reducing the thermal load and wiring complexity associated with room-temperature generators. However, the cryogenic pump sources developed thus far were …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 19
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3653994
Publisher: IEEE

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A 94-fs Jitter and −249.3-dB FoM MDLL With Background Calibration of Injection Phase and Slew-Rate Mismatch

A 94-fs Jitter and −249.3-dB FoM MDLL With Background Calibration of Injection Phase and Slew-Rate Mismatch 150 150
Author(s): Dongjun Park, Jae-Yoon Sim, Seon-Kyoo Lee

Abstract:

This article presents a ring oscillator (RO)-based multiplying delay-locked loop (MDLL) that incorporates a dual-background calibration scheme to compensate for both injection phase and slew-rate mismatches. The MDLL employs the proposed frequency/slew-rate detector (FSD) to distinguish both mismatch types by comparing the pulse widths of consecutive output clock …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3648361
Publisher: IEEE

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A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional-N PLL

A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional-N PLL 150 150
Author(s): Hongyu Lu, Nader Fathy, Patrick P. Mercier

Abstract:

This letter presents a low-jitter digital harmonic-mixing fractional- $N$ phase-locked loop (PLL) using a ring oscillator. To extend the loop bandwidth, a mixer with unity gain in the phase domain is adopted, which helps suppress phase noise of the phase detector and delta-sigma modulator. Furthermore, to reduce mixing harmonics that …

Published in: IEEE Solid-State Circuits Letters
Page(s): 57 – 60
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3654239
Publisher: IEEE

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A 0.015-mm2 0.5-V Synthesizable Hybrid PLL With Multi-Phase Linear Proportional-Gain Paths

A 0.015-mm2 0.5-V Synthesizable Hybrid PLL With Multi-Phase Linear Proportional-Gain Paths 150 150
Author(s): Qibang Sun, Liqun Feng, Woogeun Rhee, Hanjun Jiang

Abstract:

This brief presents a 0.015-mm2 0.5-V synthesizable hybrid phase locked loop (PLL). All blocks including an analog proportional-gain path can be logically or physically synthesized with digital cells and hardware languages. To mitigate the mismatch and common-mode fluctuation problems of a voltage-mode phase detector, multi-phase proportional-gain paths are designed for …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3649215
Publisher: IEEE

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